Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-01-14
2001-01-30
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S719000
Reexamination Certificate
active
06180531
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of stacked wiring layers, i.e., multilayer interconnection layers, and the present invention also relates to a manufacturing method of the semiconductor device which is suitable for forming an insulating layer to constitute the multilayer interconnection layers.
2. Description of the Related Art
With an increase in integration of ultra high semiconductor integrated circuit (hereinafter referred to as an LSI), discrete elements to be formed with a dimensional accuracy less than ¼ &mgr;m has been nowadays formed near a silicon substrate.
The LSIs exhibit no functions as a system until fine discrete elements are electrically coupled therebetween with wirings.
When the wrings to couple the individual discrete elements detour in order to avoid crossing of them, however, an area in chips occupied by the wirings increases and a wiring length increases, resulting in a wiring delay. Therefore, in order to prevent crossing points of the wirings and overlapping of them, technologies to couple the discrete elements with wirings having multi-wiring structure have been popularly employed. The multi-wiring structure is realized by arranging an insulating film between the wirings.
FIG. 3
shows a conceptional view of a multilayer interconnection. Referring to
FIG. 3
, an insulating film
31
is formed on a silicon substrate
1
. A contact hole
4
is formed to make a connection to an element formation region
2
. A contact plug
4
is formed to bury the contact hole
4
, whereby the connection of the element formation region
2
to a first wiring layer
51
is achieved.
Moreover, the connection of the first wiring layer
51
to a second wiring layer
52
is made through a via plug
61
buried in a via hole
61
opened in the insulating film
32
. The connection of the second wiring layer
52
to a third wiring layer
53
is made via a via plug
62
buried in a via hole
62
again opened in an insulating film
33
. By repeating the above-described process, it will be possible to obtain a multilayer interconnection composed of more stacked layers. Formation of the multilayer interconnection is completed when a finally formed wiring is covered with a sealing film
7
.
However, in the technology for the multilayer interconnection in which a thin insulating film is interposed between wiring layers, a large quantity of a floating capacitance between the wirings causes a wiring delay, and cross talk occurs when a signal containing high frequency components through the two wirings holding an interlayer insulating film therebetween is transmitted, resulting in occurrence of erroneous operations.
In order to prevent such wiring delay and cross talk, an increase in a distance between upper and lower wirings holding the interlayer insulating film is required, that is, a thickness of the interlayer insulating film must be set large. On the other hand, when the thickness of the interlayer insulating film is set large, a contact hole and via hole must be formed deeply. The formation of the deep contact hole and via hole makes a dry etching technique to form these holes more difficult. From this viewpoint, it is necessary to make the thickness of the interlayer insulating film thin as possible.
Hereafter, in a semiconductor integrated circuit technology to be put to a practical use after 256 megabits DRAM (dynamic random access memory), a diameter of a contact hole must be less than ¼ &mgr;m. From the viewpoint of a dry etching technique, when it is intended to make an aspect ratio, i.e., a ratio of a depth of the contact hole to a diameter thereof, at most less than 5, the thickness of the interlayer insulating film must necessarily be less than about 1 &mgr;m.
Moreover, in addition to the above-described problems of the upper and lower wiring layers interposing the interlayer insulating film, problems of wiring delay and cross talk due to an increase in a floating capacitance between wirings formed on the same surface are severer as the integration grade of the semiconductor integrated circuit increase.
The reason of this is as follows. With micronization of the semiconductor integrated circuit, an interval between the wirings reduces as well as a width of the wiring, so that the width thereof becomes necessarily equal to ¼ &mgr;m. However, it is not allowed to make the interval of the wirings larger because of the requirement for the high integration of the semiconductor integrated circuit. Therefore, the problems of the wiring delay and cross talk between the wirings disposed in the same surface level are severer than those between the upper and lower wirings interposing the interlayer insulating film, which are solved by making the thickness of the inter-layer insulating film larger.
In order to obtain the wiring delay and cross talk accurately due to the increase in the wiring capacitance, the increase in the wiring capacitance being related to the thickness of the interlayer insulating film as to the upper and lower wirings or related to the integration degree of the semiconductor integrated circuit including the wirings formed on the same surface level, it is necessary to approach the wiring delay and cross talk with means like a distributed constant circuit.
This approach to the wiring delay and cross talk will be described with reference to FIG.
1
.
FIG. 1
shows a capacitance per unit wiring length between a silicon substrate wiring and a wiring layer insulated by an oxide silicon film of a thickness H (specific dielectric constant: 3.9), disclosed by L. M. Dang et al., IEEE, Electron Device Letters, No. EDL-Vol. 2, p. 196, 1981.
In the above paper, it is disclosed that a capacitance C increases remarkably compared to a capacitance similar to a so called parallel plate, by a fringe effect as the wiring width W reduces. At the same time, the presence of the fringe effect shows the fact that the more increase in the capacitance C is brought about compared to the capacitance similar to the parallel plate when a wiring height H is large.
It seems that an insulating film disposed between a silicon substrate and a lowermost wiring as shown in
FIG. 1
is never called an interlayer insulating film. However, the problems of the wiring delay and cross talk are common to this insulating film, and, in the description of the specification for this application of the present invention, the insulating film which is formed directly on the silicon substrate to insulating electrically the wirings shall be also called an interlayer insulating film.
Furthermore, changes of the capacitance Cf per unit length between the wiring and the silicon substrate with advancement of micronization of the interval of the wirings are shown
FIG. 2
which is described in the above dissertation. Although a capacitance C
11
between the wiring and the silicon substrate reduces with the advancement of the micronization of the interval S of the wirings, a capacitance C
12
between the wirings which are adjacent to each other separated by said interval S increases. As a result, when W/H exceeds 1, the capacitance Cf per unit length between the silicon substrate and the wiring increases as the micronization advances.
Specifically, although an operation speed of the elements constituting the semiconductor integrated circuit can be increased by micronizing the elements, when the wirings connecting the elements are micronized, an operation speed of the whole of the semiconductor integrated circuit will never increase because of the increase in the floating capacitance as well as an increase in a wiring resistance.
The results shown in
FIGS. 1 and 2
are given by analyzing the floating capacitance between the silicon substrate and the wiring disposed interposing the insulating film. They are not result concerning the floating capacitance between the wirings. However, the qualitatively equal results can be obtained concerning the floating capacitance between the wiring layers. Therefore, in
Endo Kazuhiko
Matsumoto Yoshishige
Ohnishi Yoshitake
Tatsumi Toru
Brown Charlotte A.
Foley & Lardner
Kunemund Robert
NEC Corporation
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