Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-05
2003-04-08
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S760020, C324S1540PB
Reexamination Certificate
active
06545499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor manufacturing-and-inspection system, and more particularly, to a semiconductor manufacturing-and-inspection system suitable for use in subjecting semiconductor devices mounted on a burn-in board to a burn-in test, as well as to a semiconductor device manufactured through use of the semiconductor manufacturing-and-inspection system.
2. Background Art
In general, a semiconductor manufacturing-and-inspection system sometimes employs a test mode during a process for testing semiconductor devices or an accelerated test (i.e., a burn-in test) to be effected in a reliability test, in order to shorten a burn-in time. For instance, although usually only one circuit is activated during a test, a plurality of circuits are simultaneously activated through use of a test mode. Accordingly, the number of circuits to be activated per unit time is increased, thus shortening a burn-in period.
In this case, all semiconductor devices mounted on a burn-in board a reactivated simultaneously. Hence, a indicated by solid line “a” shown in
FIG. 6
, the amount of current dissipated by a semiconductor device becomes large and exceeds the current supply capability of a burn-in apparatus. As a result, anomalies arise in the burn-in apparatus, or a limitation is imposed on the number of semiconductor devices to be mounted on the burn-in board.
As a countermeasure against such problems, Japanese Patent Application Laid-Open No. 145213/1999 describes use of a burn-in timer circuit provided in a semiconductor device, in order to reduce the current which flows instantaneously when a plurality of chips operate at the same timing during full wafer measurement and inspection operations. A burn-in operation cycle is determined by apparatus of a clock cycle of the burn-in timer circuit. Since variations in manufacturing process parameter result in variations in clock cycle in different locations over a wafer, a clock cycle differs from one semiconductor chip to another. Hence, an electric current flowing instantaneously during a burn-in test can be diminished.
However, an apparatus employing such a related-art technique involves incorporation of a burn-in timer circuit in a semiconductor device. Hence, the area occupied by semiconductor chips becomes larger, and the number of semiconductor chips which can be manufactured from a single wafer is diminished.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the drawback of the related-art technique and is aimed at providing a semiconductor manufacturing-and-inspection system which readily enables conduction of a burn-in test without imposing a limitation on the number of semiconductor devices to be mounted on a burn-in board, as well as a semiconductor device manufactured through use of the apparatus.
According to one aspect of the present invention, a semiconductor manufacturing-and-inspection system which tests semiconductor devices provided in a plurality of areas on a burn-in board through use of a burn-in apparatus comprises signal generation apparatus for supplying a drive signal to the semiconductor devices provided in the plurality of areas, delay apparatus which is provided for one part a plurality of drive signals output from the signal generation apparatus and delays the part of drive signals relative to the other part of drive signals, and control apparatus for controlling the delaying operation of the delay apparatus.
According to the present invention, the peak of the current dissipated by the semiconductor devices is dispersed and can be suppressed to a level below the current supply capability of the burn-in apparatus. Hence, there is eliminated a necessity for modifying a delay provided in a determination system of the burn-in apparatus. A burn-in test can be readily performed without involvement of anomalies arising in the burn-in apparatus or limitations on the number of semiconductor devices mounted on the burn-in board.
According to another aspect of the present invention, a semiconductor device is manufactured through use of the semiconductor manufacturing-and-inspection system described above.
The present invention provides an advantage of the ability to provide a highly-reliable semiconductor device of high quality.
REFERENCES:
patent: 5327076 (1994-07-01), Bailey
patent: 5390129 (1995-02-01), Rhodes
patent: 11-145213 (1999-05-01), None
Cuneo Kamand
McDermott & Will & Emery
Nguyen Tung X.
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