Semiconductor light emitting device and method

Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – With particular semiconductor material

Reexamination Certificate

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C257S104000

Reexamination Certificate

active

06646292

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to light emitting semiconductor structures and methods of making same and, more particularly, to devices and methods employing group III-V nitride semiconductors and to improving the manufacture and the operation thereof.
BACKGROUND OF THE INVENTION
Light emitting semiconductors which emit in several regions of the visible spectrum, for example group III-V semiconductors such as aluminum gallium arsenide and gallium phosphide, have achieved commercial acceptance for various applications. However, for applications which require blue or green light, for example green to be used for traffic signal lights or blue for a component of a red-green-blue primary color combination to be used for white lighting, efficient semiconductor light emitters have been sought for shorter visible wavelengths. If such solid state light emitting sources were available at reasonable cost, many lighting applications could benefit from the reliability and low energy consumption that characterize semiconductor operation. Short wavelength devices also hold promise of providing increased storage capacity on storage media, due to the ability to obtain smaller spot sizes for writing and reading on the media.
A type of short wavelength light emitting devices that has direct energy bandgap, and has shown excellent promise, is based on group III-V nitride semiconductors, which include substances such as GaN, AlN, InN, AlInN, GaInN, AlGaN, AlInGaN, BAlN, BInN, BGaN, and BAlGaInN, among others. [These are also sometimes referred to as III-nitride semiconductors.] An example of a light emitting device of this type is set forth in European Patent Publication EP 0926744, which discloses a light emitting device that has an active region between an n-type layer of III-nitride semiconductor and a p-type layer of III-nitride semiconductor. An electrical potential applied across the n and p layers of the diode structure causes generation of photons at the active region by recombination of holes and electrons. The wallplug efficiency of the light emitting diode (LED) structure is defined by the optical power emitted by the device per unit of electric power. To maximize efficiency, both the light generated per watt of drive power and the amount of light exiting from the LED in a useful direction are considered.
As noted in the referenced EP Patent Publication, considerable effort has been expended in prior art approaches to maximize the light that is generated from the active region. The resistance of the p-type III-nitride semiconductor layer is much higher than the resistance of the n-type III-nitride semiconductor layer. The p-electrode typically spans essentially the entire active area to spread current uniformly to the junction with low electrical resistance. Although this increase in size of the p-electrode may increase the amount of light available from the active region, it can decrease the fraction of light that exits the device, since much of the light must pass through the p-electrode. The transmittance of the p-electrode can be increased by making the electrode thin or providing it with apertures (see, for example copending U.S. patent application Ser. No. 09/151,554, filed Sep. 11, 1998), but even these somewhat transmissive electrodes can absorb a significant amount of light, and their light transmission characteristics tend to trade-off against electrical operating efficiency, such as by compromising the uniform current density desired for the active region.
As noted in the above-referenced parent applications hereof, because III-nitride substrates are not commercially available, growth of III-nitride LEDs is typically implemented on non-lattice matched substrates such as sapphire or silicon carbide.
In so called “flip-chip” or “epitaxy side-down” configurations, the problem of light transmission through the electrodes is eliminated, as the device is flipped over and mounted with the epitaxy side down so that the light escapes predominantly through the substrate. The most common substrate is sapphire, but the relatively low refractive index of sapphire (n~1.8) limits performance due to index mismatch with the epitaxial region (which has n~2.4) that results in a “waveguiding” effect on some of the light generated at the active region. As described further hereinbelow, this portion of the light is trapped in the epitaxial region for one or more reflections as a significant fraction of the light energy is lost. Roughening of the sapphire/epilayer interface can help somewhat, but is of limited effectiveness and can have other disadvantages. Reference can be made to U.S. Pat. No. 6,091,085.
The above-referenced parent applications hereof describe some examples of prior art approaches that employ substrates of sapphire or of conductive silicon carbide, and these are summarized briefly as follows:
Nakamura et al. U.S. Pat. No. 5,563,422, Inoue et al. European Patent 091577A1, Kondoh et al. European Patent 0926744A2, and Mensz et al., Electronic Letters 33 (24) pp. 2066-2068, 1997, each disclose III-nitride LEDs formed on sapphire substrates. Nakamura et al. describes an epitaxy side-up configuration, and the others describe inverted (flip-chip) configurations. All of these approaches tend to be performance limited by, inter alia, the above-noted effect of a portion of the light being waveguided and trapped because of the sapphire/epitaxy index mismatch.
The published PCT Application WO96/09653 (Edmond et al.) discloses an embodiment with a vertical injection III-nitride LED on a conducting SiC substrate. A conductive buffer layer is required for Ohmic conduction from the III-nitride layers to the SiC substrate. The growth conditions required for a conductive buffer layer limits the growth conditions available for subsequent layers and thus restricts the quality of the III-nitride active region layers. Also, the conductive buffer layer may introduce optical loss mechanisms that limit light extraction efficiency. Furthermore, the SiC substrate must be doped to provide high electrical conductivity (p<0.2 &OHgr;-cm) for low series resistance. Optical absorption resulting from SiC substrate dopants limits the light extraction efficiency of the device. These conditions result in a trade-off between series resistance and light extraction efficiency and serve to limit the electrical-to-optical power conversion efficiency of the LED.
Small-area surface-mount LED chips are attractive for many applications such as contour strip-lighting and backlighting. For these devices, high light-generating capability is not required, but the devices should be efficient and inexpensive. Therefore, it is desirable for the devices to be as small as possible, with efficient use of the active region area. Also, these surface-mount devices should be capable of mounting to a package without the use of wirebonds. Conventional III-nitride devices most commonly employ sapphire substrates. These substrates are relatively inexpensive and suitable for the growth of good quality nitride films. Because the substrate is insulating, both p and n contacts are made on the same surface of the LED chip. This facilitates attaching the LED to a submount or package in the flip-chip approach that was first noted above, such that both p and n bondpads are electrically interconnected to the external package without wirebonds. However, in addition to the previously mentioned problem of light loss due to waveguiding, the sapphire substrate is difficult to dice in sizes less than 400×400 um{circumflex over ( )}2, making it difficult to fabricate low-cost surface mount LED chip devices. Scribing-and-breaking, or sawing, the sapphire at these dimensions results in undesirably low yields and is unfavorable for high-volume manufacturing.
An alternative approach to fabricating III-nitride LEDs employs a conductive SiC substrate, as in the above-summarized Edmond et al. PCT published Application. The device growth includes a conductive buffer layer that enables vertical injection operation. The device has th

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