Semiconductor level shifter circuit

Details Semiconductor level shifter circuit Semiconductor level shifter circuit

2002-01-22

2003-11-11

Tran, Michael Thanh (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189110

Reexamination Certificate

active

06646918

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor circuit and more particularly to a semiconductor circuit that can be used as a level shifter in a semiconductor device such as a non-volatile memory.
BACKGROUND OF THE INVENTION
Level shifters or level translators are used to receive logic signals at one voltage range and produce logic signals having a higher voltage range.
Referring now to
FIG. 7
, a conventional level shifter is set forth in a circuit schematic diagram and given the general reference character
700
.
Conventional level shifter
700
receives an input signal IN having a high logic level provided by a Vcc power supply and provides an output signals (BOUT and TOUT) that has a high logic level provided by a Vpp power supply. Both the input signal IN and output signals (BOUT and TOUT) have a low logic level at the ground potential. The Vpp power supply is provided by boosting the Vcc voltage using a booster circuit. In this way, conventional level shifter
700
receives an input signal having a voltage range between ground and Vcc and provides an output signal having a voltage range between ground and Vpp.
Conventional level shifter
700
includes p-channel MOS (metal-oxide-semiconductor) transistors (P
101
and P
102
), n-channel MOS transistors (N
101
and N
102
), and in inverter V
101
.
Transistor P
101
has a source and a body (substrate or well) connected to the power supply terminal, a drain connected to output signal BOUT, and a gate connected to output signal TOUT. Output signal TOUT is a true output signal and output signal BOUT is a complementary output signal. Transistor P
102
has a source and a body (substrate or well) connected to the power supply terminal, a drain connected to output signal TOUT, and a gate connected to output signal BOUT.
Transistor N
101
has a source and a body (substrate or well) connected to ground, a drain connected to output signal BOUT, and a gate connected to receive input signal IN. Transistor N
102
has a source and a body (substrate or well) connected to ground, a drain connected to output signal TOUT, and a gate connected to receive signal INB. Inverter V
101
received input signal IN at an input and provides signal INB as an output.
Output signal TOUT is of the same logic level as input signal IN. Output signal BOUT has a logic level that is inverted with respect to input signal IN.
The operation of conventional level shifter
700
will now be described.
When input signal IN is low, transistor N
101
is turned off and inverter V
101
applies a high to the gate of transistor N
102
. Thus, transistor N
102
is turned on and pulls output signal TOUT to ground. With output signal TOUT low, transistor P
101
is turned on and pulls output signal BOUT to the power supply potential. With output signal POUT being at the power supply potential transistor P
102
is turned off. Thus, when inputs signal IN is low, output signal BOUT is at the power supply potential (VPP) or high and output signal TOUT is at ground or low.
When input signal IN is changed from low to high, transistor N
101
is turned on and inverter V
101
applies a low to the gate of transistor N
102
. Thus, transistor N
102
is turned off. With transistor N
101
turned on, output signal BOUT is pulled low. As output signal BOUT is pulled low, transistor P
102
is turned on and pulls output signal TOUT toward the power supply potential or high. With output signal TOUT being at the power supply potential transistor P
101
is turned off. Thus, when inputs signal IN is high, output signal TOUT is at the power supply potential (VPP) or high and output signal BOUT is at ground or low.
If a level shifter is only to provide level shifting from the Vcc voltage to the Vpp voltage, then conventional level shifter
700
may be sufficient.
However, in some applications, a level shifter needs to provide level shifting from the Vcc voltage to the Vpp voltage during certain operations and not provide level shifting (keep the output signals supplied by the Vcc voltage) at all in other operations. One such application is in a flash memory where a Vpp voltage level may be applied to a memory cell in a write, but data may be read at the Vcc voltage level. It can be difficult to design a level shifter that can operate at the same switching speed for both voltage output levels (Vpp and Vcc). Problems for this case will now be discussed.
The conventional example provides a pull down with n-channel MOS transistors and a pull up with p-channel MOS transistors. When the p-channel MOS transistor is beginning to pull up an output signal, Vds>Vgs−Vtp in the p-channel MOS transistor, where Vds is the drain-source voltage, Vgs is the gate-source voltage and Vtp is the threshold voltage of the p-channel MOS transistor. With Vds>Vgs−Vtp, the p-channel MOS transistor operates in the saturation region.
Also, when the n-channel MOS transistor is beginning to pull down an output signal, Vds>Vgs−Vtn in the n-channel MOS transistor, where Vds is the drain-source voltage, Vgs is the gate-source voltage and Vtn is the threshold voltage of the n-channel MOS transistor. With Vds>Vgs−Vtn, the n-channel MOS transistor operates in the saturation region.
When in the saturation region the drain current Id of a MOS transistor is obtained by the equation:
Id=K(V−Vt)
2
×W/L, where K is a constant obtained by the channel mobility and the dielectric constant of the oxide film, W is the channel width of the MOS transistor, and L is the channel length of the MOS transistor. V represents the value of the voltage applied between the gate and the source of the MOS transistor and Vt is the threshold voltage of the MOS transistor.
When conventional level shifter
700
has the Vcc supply applied to the power supply terminal, the voltage applied between the gate and the source of the p-channel MOS transistors (P
101
or P
102
) is much lower than when conventional level shifter
700
has the Vpp supply applied to the power supply terminal. Thus, the drain current of the p-channel MOS transistors (P
101
or P
102
will be much lower when conventional level shifter
700
has the Vcc supply applied to the power supply terminal than when Vpp is supplied to the power supply terminal. If the transistor size (channel width Wp and Wn) of the respective transistors (N
101
, N
102
, P
101
, and P
102
) in conventional level shifter
700
are designed in accordance with the operation at the Vpp voltage, operating characteristics at the Vcc voltage may suffer.
In the n-channel MOS transistors (N
101
and N
102
), the gate-source voltage (Vgs) does not change in accordance with which power supply (Vdd or Vpp) is connected to the power supply terminal and the drain current Id is the same for both cases. Therefore, the drain current of the p-channel MOS transistors is reduced when Vcc is supplied to the power supply terminal which makes the output signals (BOUT and TOUT) rise slower than when Vpp is supplied to the power supply terminal.
On the other hand, if the respective transistors in conventional level shifter
700
are optimally designed in accordance with Vcc being supplied to the power supply terminal, the n-channel MOS transistors may not be able to supply sufficient current to overcome the p-channel MOS transistors when Vpp is supplied to the power supply terminal. Therefore, when the output signal is changed from high to low, the p-channel MOS transistor, which is turned on, may not be quickly overpowered by the n-channel MOS transistor which can increase the high to low switching time of the output signal. With an increased high to low switching time, the p-channel MOS transistor stays turned on longer and current can flow through from the power supply terminal to ground which increases current consumption.
Also, conventional level shifter
700
may not be able to lower the level of an output signal to ground unless the channel width (Wn) of the n-channel MOS transistors have a large enough value to provide sufficient driving capabilities. As a re

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