Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal
Reexamination Certificate
1998-08-24
2001-07-03
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
C257S048000
Reexamination Certificate
active
06255707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor lasers having a greater degree of reliability and more particularly to structures that enable semiconductor lasers to be tested for reliability. The invention further relates to methods for testing the reliability of semiconductor lasers in wafer or chip form. The invention also relates to methods for the fabrication of semiconductor lasers which include the use of reliability tests in the fabrication process where the reliability tests include measuring the voltage drop or drops across one or more levels of a laser structure during the passage of current through the structure.
Semiconductor lasers are used in a variety of applications that require a high level of reliability in the devices under normal use for specified periods of time. Reliability is of a special concern when the lasers are used in communications systems which are difficult to repair or replace, such as undersea cable. The cost of ensuring reliability of the semiconductor laser is a substantial part of the final cost of a laser transmitter or pump module. Thus, if the reliability of a laser is assured on the basis of tests performed on individual lasers after the full fabrication of the semiconductor laser devices or other incorporation of the devices in modules or packages, the cost of reliability assurance will be excessive due to the cost of handling and testing individual devices as well as the loss of materials and labor invested in the fabrication of those semiconductor laser devices which ultimately fail. The present invention overcomes these drawbacks.
In optical semiconductor devices, excitation is introduced by electron (hole) injection to the conduction (valence) band through current biasing at the p-n junction. The voltage drop across a semiconductor junction (either a p-n junction or a Schottky Metal-Semiconductor junction) depends on the impurities present in the junction volume itself. Any impurity which tends to counteract the effect of the dopants or which provides current leakage paths will cause a deviation of the voltage across the junction from the value it would have in the absence of the impurity. Impurities which cause reliability problems tend to be those which diffuse rapidly and these impurities will cause the junction voltage to change with time when the material is stressed very hard by the passage of substantial current. In addition, morphological changes in either the metalsemiconductor interface or the p-n junctions of the semiconductor device under bias will also cause changes in the voltage which are accelerated by high currents.
The theory of semiconductor laser reliability has been developed over many years since the invention of the semiconductor laser. For most lasers, the most important aspect of reliability is the change in efficiency of the laser. The problem of reliability of semiconductor lasers have been discussed in many articles, such as, for example, Aoyagi et al., “Threshold Current Density Dependence on p-doping in AlGaInP Laser,” SPIE Laser Diode Technology and Applications II, Vol. 1219 1990; Sakaki et al., “Doping Optimization in InGaAsP DH Lasers and Improved Characteristics in BH Lasers Grown by MOVPE,” Journal of Crystal Growth, Vol. 93 pp. 838-843, 1988; Zemel and Gallant, “Carrier Lifetime in InP/InGaAs/Inp by Open-Circuit Voltage and Photoluminescence Decay,” Journal of Applied Physics, Vol. 78 pg. 1094, 1995 and Ikegami et al., “Stress Test on 1.3 &mgr;m Buried-Heterostructure Laser Diode,” Electronics Letters, Vol. 19 pg. 382, 1983, which are herein incorporated by reference.
While not wishing to be bound by theory, it is believed that changes in this performance indicator may be due to non-radiative recombination centers (NRRCs) in the active region. These NRRCs result in changes in light output at a constant current, an increase in the threshold current of the laser, or an increase in the current required to create a stated optical power at the output facet. Non-radiative recombination centers may be induced by a variety of original causes, including diffusion of impurities into the active layer from regions outside of the active layer during processing. Diffusion of these NRRCs may be assisted by electrical fields, currents or by the heat energy generated by current flow. Additionally, the NRRCs may be generated during manufacture by improper processing such as excess alloying of the metal contacts near the active region or by the incorporation of impurities such as copper which are known to act as NRRCs. In direct band-gap semiconductors, NRRCs occur mainly as a result of crystalline defects or impurities. Additionally, NRRCs occur due to spiking of metal through the layers of the laser. This spiking is known to cause laser degradation and failure.
Since voltage can be measured very accurately, changes in voltage the junctions of the semiconductor device during the passage of current can be detected even when the change is very small. Thus, it is an object of the present invention to measure the changes in the voltage drop between the metal and the cap layer. The voltage drop between these layers correlates to changes in threshold current, which is a standard indicator of device reliability. Further, changes in voltage drops may be greatly accelerated by the passage of high currents through the device structure and these changes may be used to predict laser reliability.
Because the present invention relies on principals of device physics which are well-known to those skilled in the art, it is possible to correlate the present invention tb the measurement of other voltage drops in the stack of layers making up the device, including the drop across the first heterojunction, the device p-n junction and the junctions between the laser layers and the blocking layer.
The economic impact of the wafer level reliability testing of the present invention can be estimated by considering that much of the cost of a packaged laser is in the testing of the laser. Further, threats to laser reliability are often associated with errors in wafer fabrication which can be eliminated by the present invention.
2. Description of the Related Art
The prior art includes descriptions of the causes of failure of reliability of semiconductor lasers and other semiconductor devices, and the use of wafer level testing as a part of the fabrication of integrated circuits, but no use of wafer level testing incorporating a voltage test point as part of the fabrication sequence of a laser and no description of laser structures incorporating voltage test points.
In the past, it has been the practice to provide a test structure on the edge of a wafer or substrate to measure changes in the electrical properties. However, due to the high levels of electrical noise present in many manufacturing processes, it was usually necessary to halt the process and remove the wafer or substrate from the process in order to make the measurement. Therefore the process was interrupted and throughput was diminished. Further, the accuracy of the measurement was compromised by the need to re-start the process.
Various methods for detecting defects in, and thus testing the future reliability of, thin film insulators in integrated circuits, particularly insulators in memory devices, such as EPROMs, EEPROMs, DRAMs, and other products with nonvolatile memory, have been discussed in the related arts. Unfortunately, existing wafer-level-reliability monitors of oxide breakdown voltage are not good predictors of laser reliability, and they are slow and destructive. Further, these methods have been limited to memory devices and not the semiconductor lasers of the present invention.
One type of reliability testing for memory cells is called “burn-in”. In a burn-in test, the integrated circuit is subjected to elevated temperatures before performing functional tests on the integrated circuit. An integrated circuit undergoing a burn-in test is subjected to an elevated temperature for several hours. Because a large amou
Bylsma Richard B.
Derkits, Jr. Gustav E.
Heffner William R.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Lucent Technologies - Inc.
Potter Roy
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