Semiconductor isolation process to minimize weak oxide problems

Details Semiconductor isolation process to minimize weak oxide problems Semiconductor isolation process to minimize weak oxide problems

1999-11-16

2001-10-30

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S297000, C438S298000, C438S426000, C438S440000, C257S647000

Reexamination Certificate

active

06309949

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to methods for forming integrated circuit chips, and more particularly, to a method for substantially eliminating tunnel oxide thinning and weak oxide problems resulting from the trench-forming isolation process.
An integrated circuit chip comprises an array of devices formed in a semiconductor substrate, with the contacts for these devices interconnected by patterns of conductive wires. These devices must be isolated from each other in order to properly function. One method used in the art to isolate CMOS circuits is the use of isolation trenches with vertical sidewalls. Such isolation trenches are advantageous in that they have a significantly smaller width than standard LOCOS isolation field oxide regions of the same depth. However, it has been discovered that the dry etching techniques utilized to form the deep isolation trenches tend to damage the silicon at the top of the mesas of silicon bordering the isolation trench. Specifically, the plasma molecules bombarding the silicon damage the silicon lattice resulting in a rough surface. In succeeding steps when tunnel oxide is grown on top of the silicon mesas, the oxide quality at the damaged edges of the mesas is thin and relatively weak. If the gate region for transistors is formed in the damaged silicon below these weak oxide areas, then there is a high potential for shorting of the gate through the oxide. This is a particular problem for floating gate structures formed in integrated circuits. Such floating gate structures receive data by means of electron tunnelling across a tunnel oxide up to the gate. It has been discovered that if a corner of the tunnel oxide contains defect sites caused by a damaged silicon layer thereunder, then electrons can leak back out of the gate through these defect sites, thereby losing the data on the gate and causing data retention problems. Additionally, if substantial electron tunneling occurs at the location of the thin oxide at a corner (which would tend to occur since the thinness of the corner makes that location the path of least resistance), then a tunnel oxide breakdown and short at that point can occur. This presents a significant reliability problem for chips utilizing such an isolation process.
SUMMARY OF THE INVENTION
Briefly, the present invention comprises a process for forming an isolation region while substantially eliminating weak oxide effects, comprising the steps of: obtaining a semiconductor substrate patterned with a plurality of mesas with sidewalls, with semiconductor substrate exposed in areas between the mesas, each of the mesas comprising at least a first insulator layer and a second different insulator later thereover; forming a trench between the mesas into the exposed semiconductor substrate; removing a lateral portion of the first insulator layer exposed at the sidewalls of the mesas to thereby undercut the second insulator layer at its sidewall edges; forming an oxide layer on exposed areas of the semiconductor substrate below the undercut of the second insulator layer; and filling the trench with an insulator material.
In a preferred embodiment of the present invention, after the lateral portion removal step, and before the oxide forming step, implanting material into an area in the semiconductor substrate exposed below the undercut edges of the second insulator material where the lateral portion of the first insulator layer is removed.
In a yet further aspect of this preferred embodiment, the implanting step comprises the step of implanting nitrogen atoms and ions using a large angle of implant.
In a further aspect of the present invention, the first insulator layer is an oxide layer and the second insulator layer is a nitride layer and the semiconductor substrate is silicon.
In a further aspect of the invention, the inventive process comprises the steps of: after the trench filling step chemical-mechanical polishing down to approximately the top of the second insulator layer; removing the first and second insulator layers to expose the semiconductor substrate thereunder; and forming a tunnel oxide on the exposed semiconductor substrate.
In a further aspect of the invention, a semiconductor isolation structure is provided comprising a semiconductor substrate with a plurality of trenches formed therein with substantially vertical sidewalls, with the plurality of trenches defining at least one mesa of semiconductor material; wherein the top corner of the mesas has been converted to an oxide; and an insulator material filling the plurality of trenches.
In a yet further aspect of this embodiment of the invention, the top corner of the mesa contains a heavy ion implant.
In a yet further aspect of the invention, the top corner of the mesa contains a nitrogen implant.


REFERENCES:
patent: 4576834 (1986-03-01), Sobczak
patent: 4580330 (1986-04-01), Pollack et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5084071 (1992-01-01), Nenadic et al.
patent: 5372950 (1994-12-01), Kim et al.
patent: 5410176 (1995-04-01), Liou et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5498891 (1996-03-01), Sato
patent: 5668403 (1997-09-01), Kunikiyo
patent: 5767000 (1998-06-01), Fulford, Jr. et al.
patent: 5858866 (1999-01-01), Berry et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5891787 (1999-04-01), Gardner et al.
patent: 5937308 (1999-08-01), Gardner et al.
patent: 5985735 (1999-11-01), Moon et al.
patent: 6008107 (1999-12-01), Pierce et al.

Affiliated with

Also associated with

Rating

Semiconductor isolation process to minimize weak oxide problems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor isolation process to minimize weak oxide problems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor isolation process to minimize weak oxide problems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2607210