Semiconductor isolation method

Details Semiconductor isolation method Semiconductor isolation method

1996-11-07

1998-01-27

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438426, 438424, 438298, H01L 2176

Patent

active

057122059

ABSTRACT:
The present invention relates to a semiconductor isolation method for high density semiconductor(devices of which the isolation pitch is below 0.5 .mu.m. The present invention provides the semiconductor isolation method to improve the isolating characteristics of the semiconductor device by separately performing the isolation process for the area where the isolation pitch is wide from the area where it is narrow. In accordance with the present invention, there is disclosed a semiconductor isolation method including the steps for forming a pad oxide layer and a nitride layer on a semiconductor substrate having an area of relatively narrow isolation pitch and an area of relatively wide isolation pitch, selectively etching the nitride layer and the pad oxide layer on the area of relatively narrow isolation pitch to expose the semiconductor substrate thereunder and forming a trench into a predetermined area of the exposed semiconductor substrate, forming an insulating layer on the resulting structure, removing the insulating layer, whereby the insulating layer remains in the trench, selectively etching the nitride layer on the area of relatively wide isolation pitch, and forming a field oxide on the area where the nitride layer is removed.

REFERENCES:
patent: 4980311 (1990-12-01), Namose
patent: 5112772 (1992-05-01), Wilson et al.
patent: 5116779 (1992-05-01), Iguchi
patent: 5369051 (1994-11-01), Rao et al.
patent: 5455438 (1995-10-01), Hashimoto et al.

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