Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-05-31
2004-05-11
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S400000, C438S424000
Reexamination Certificate
active
06734080
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit design and semiconductor chip fabrication. More particularly, the present invention relates to an efficient and effective system and method for depositing tetraethylorthosilicate on a wafer.
BACKGROUND OF THE INVENTION
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include integrated circuits. Integrated circuit fabrication usually involves multi-step processes that attempt to produce precise components that operate properly. Many integrated circuit processes involve repeated deposition and removal of material layers to fabricate components and it is often very difficult to achieve optimized results within requisite narrow tolerances. Inadequate removal of some material layers can have detrimental impacts on the performance of the final product.
Semiconductor integrated circuit manufacturing efforts are usually complicated by ever increasing demands for greater functionality. More complicated circuits are usually required to satisfy the demand for greater functionality. For example, there is usually a proportional relationship between the number of components included in an integrated circuit and the functionality, integrated circuits with more components typically provide greater functionality. However, including more components within an integrated circuit often requires the components to be densely packed in relatively small areas and reliably packing a lot of components in relatively small areas of an IC is usually very difficult.
One traditional focus for achieving greater densities has been directed towards reducing the size of isolation regions around individual components (e.g., transistors). The components of an integrated circuit are usually fabricated on a single silicon substrate and maintaining both the integrity of the system as a whole as well as the individual basic device characteristics is very important for proper operation. Proper isolation is very helpful in achieving these objectives and without proper device isolation there is a tendency for detrimental interactions to occur. For example, placement of more components in smaller spaces by reducing the separation between adjacent components increases the probabilities of failures associated with parasitic conduction paths and latch up. Proper isolation significantly reduces the probability of parasitic conduction and latch up. Thus, it is important for integrated circuit fabrication technologies to provide an advantageous balance between isolation integrity and increased component density.
Shallow trench isolation (STI) in an integrated circuit fabrication technology that usually offers significant potential for maintaining isolation integrity and increasing component density. STI offers many advantages over other methods, such as local oxidation of silicon (LOCOS), since STI has minimal field encroachment, good latch-up immunity, smooth planarity, and reduced junction capacitance. It is important for basic device characteristics to be as close to ideal as possible and STI helps by reducing parasitic conduction paths and series resistances, maintaining threshold voltage control, and minimizing the leakage current of the device.
STI usually consists of a trench filled with an isolation material such as oxide. It is important for oxide layers to be accurately applied to ensure proper isolation without defects. It is also desirable for the oxide application to be efficient and low cost. Deposition of high quality oxide film with the ability to fill very narrow gaps uniformly across a wafer can be challenging. Tetraethylorthosilicate (TEOS) deposition provides many advantages that facilitates the pursuit of these objectives. One advantage of TEOS is its ability to conform to underlying topography. TOES is usually applied in a liquid form and has characteristics that enable it to accurately fill small and large trenches. However, TEOS techniques also usually results in oxide overfill that needs to be removed in order for the device to work correctly. Thus, STI techniques also typically involve material removal steps that tend to increase the fabrication complexity.
Traditional STI excess isolation material removal processes usually involves numerous technical and economic challenges due to adverse impacts associated with earlier process steps. Material removal processes such as chemical mechanical polishing (CMP) typically encounter problems that make it difficult to achieve accurate material removal and planarization in STI applications. For example, the amount of material removed during a chemical mechanical polishing (CMP) process usually depends upon the component pattern density of an active area formed in earlier process steps. Differences in density typically cause uneven polishing within a die and across a wafer often resulting in excessive and/or insufficient removal in some areas. Some manufacturers attempt partial removal of excess insulating material in densely configured areas to compensate for the adverse impacts on STI CMP due to changes in component density in different areas of a semiconductor wafer. However, these activities usually introduce additional complications for a STI CMP process. For example, the partial removal of excess insulating material in some areas usually results in significant and abrupt topographical differences between the areas.
One common detrimental topographical impact that occurs when manufactures attempt traditional partial material removal approaches to addressing component density impacts on CMP is the creation of significant spikes. The significant spikes are often in excess of 5000 Angstroms tall. While CMP is often efficient at removing excess material and planarizing the wafer to provide a smooth surface, significant and abrupt spikes that occur in traditional systems usually significantly impact CMP processes. The spikes result in uneven polishing and make it difficult to gauge the rate at which the excess insulating material (e.g., TEOS) is being removed during polishing. For example, spike height differences of excess oxide between large and small source/drain active areas make it difficult to adequately polish the overfill oxide on top of the small dimension active region without excessively polishing the large source/ drain active areas. However, leaving overfill oxide over the small source/drain active regions further complicates the manufacturing processes by increasing the difficulty of removing the protective silicon nitride layer, resulting in a residual silicon nitride problem. Inadequate oxide removal makes removal of the sacrificial nitride layer extremely difficult, thus neutralizing the active area. The residual silicon nitride problem can result in significant yield degradation. Attempts to address the problem by brute force polishing efforts can easily result in over polishing. Over polishing leads to excessive nitride erosion and trench oxide neutralizing the active area. Therefore the ability to precisely remove excess insulating STI oxide in convenient and efficient manner is very important.
SUMMARY OF THE INVENTION
A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is depos
Wang John Jianshi
Yang Nian
Yang Tien-Chun
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