Semiconductor interconnection line and method of forming the...

Details Semiconductor interconnection line and method of forming the... Semiconductor interconnection line and method of forming the...

2011-06-14

2011-06-14

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S734000

Reexamination Certificate

active

07960839

ABSTRACT:
An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.

REFERENCES:
patent: 5939788 (1999-08-01), McTeer
patent: 6084304 (2000-07-01), Huang et al.
patent: 6559548 (2003-05-01), Matsunaga et al.
patent: 6747355 (2004-06-01), Abiru et al.
patent: 6879042 (2005-04-01), Ohto et al.
patent: 7056820 (2006-06-01), Cole et al.
patent: 7223686 (2007-05-01), Bae

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