Semiconductor interconnect method and structure for high tempera

Details Semiconductor interconnect method and structure for high tempera Semiconductor interconnect method and structure for high tempera

1995-12-04

1997-09-30

Picardat, Kevin

Fishing, trapping, and vermin destroying

437182, 437205, H01L 2160

Patent

active

056725469

ABSTRACT:
A method for interconnecting at least one semiconductor chip (14 or 36) having chip pads (16 or 38) includes applying a removable polymer layer (22 or 44) over the chip; forming vias (26 or 50) in the polymer layer aligned with predetermined chip pads; depositing a pattern of electrical conductors (28 or 52) over the polymer layer and into the vias; and removing the polymer layer. Prior to applying the polymer layer, the chip can be attached to a substrate by attaching a backside of the chip in a substrate chip well using a high temperature chip attach material (12) or by inserting the chip in a through hole of the substrate and applying a metallization plane (54) supporting the backside of the chip and at least a portion of the substrate. The substrate can have substrate metallization (18 or 42) substantially planar to the chip pads with the step of applying the polymer layer over the at least one semiconductor chip including applying the removable polymer layer over the substrate, and the step of forming vias in the polymer layer including forming vias aligned with predetermined portions of the substrate metallization.

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