Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
1999-01-28
2002-04-09
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S208000, C257S241000, C257S249000, C257S331000, C257S365000, C257S392000
Reexamination Certificate
active
06369412
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor device and a semiconductor integrated circuit device comprising the same, and more particularly, to a semiconductor integrated circuit device having transistors which are arbitrarily connected to each other and the structure of a basic cell constituting the same.
BACKGROUND OF THE INVENTION
Conventionally, in order to rapidly cope with a request from a customer, a master slice system for uniformly performing design of an LSI (Large Scale Integrated Circuit) to diffusion processing in advance, and performing only later circuit wiring for each type has been well known. The master slice system has advantages suitable for the production of few-of-a-kind LSIs, for example, shortening of a period of development and reduction of costs of development.
The semiconductor integrated circuit device of a master slice system is realized by connecting a plurality of basic cells arranged in a matrix shape or in one direction in conformity to specifications of its finished product.
For example, the structure of a general basic cell carried on a semiconductor integrated circuit device of a master slice system as described in JP-A-5-630465 is illustrated in FIG.
11
.
As shown in
FIG. 11
, a basic cell
100
is constituted by gate electrodes
101
and
102
of a P-type MOS (Metal Oxide Semiconductor) transistor, a P-type impurity diffusion region
103
to be a drain terminal or a source terminal of the P-type MOS transistor, gate electrodes
104
and
105
of an N-type MOS transistor, an N-type impurity diffusion region
106
to be a drain terminal or a source terminal of the N-type MOS transistor, and two power supply interconnections
107
and
108
.
In the semiconductor integrated circuit device of the master slice type, the plurality of basic cells
100
each having such a structure are arranged on a semiconductor substrate. The gate length L of each of the transistors in each of the basic cells
100
greatly affects the performance and the cost of the semiconductor integrated circuit device. That is, the shorter the gate length L of each of the transistors is, the higher the speed of the transistor can be made. Further, it is possible to realize a circuit on the same scale by an LSI having a small area by improving its device density.
By reducing the gate length L of each of the transistors, therefore, the semiconductor integrated circuit device is increased in scale, increased in integration density, and increased in speed. In recent years, the reduction in the gate length L of each of the transistors has progressed, for example, 0.5 &mgr;M, 0.35 &mgr;m, and 0.25 &mgr;m. Even in the semiconductor integrated circuit device of the master slice type, the gate length L of the P-type MOS transistor and the N-type MOS transistor which are formed in each of the basic cells
100
is set to the minimum size.
As described in the foregoing, if in the semiconductor integrated circuit device of the master slice type, the basic cell having the gate length L of the minimum size is used, the semiconductor integrated circuit device can be increased in speed and increased in integration density.
If the gate length of the transistor is reduced, however, power consumption is increased by the increase in a leak current, and the effect of variations in a finning process is increased. For example, when the variations in the gate length are the same, the smaller the gate length is, the larger the ratio of the variations in the gate length to the normal gate length is, so that the larger the effect of the process variations on device characteristics is. As a result, the yield of the semiconductor integrated circuit device is reduced. There also occurs a case where margin must be provided to actual device operations in consideration of the process variations. As a result, the performance of the semiconductor integrated circuit device is reduced.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a semiconductor integrated circuit device which can achieve low power consumption while achieving high speed and high integration density, and the yield and the performance of which can be prevented from being reduced by process variations.
A semiconductor integrated circuit device according to the present invention comprises a substrate, and a plurality of basic cells formed on the substrate, each of the plurality of basic cells comprising one or more transistors, the one or more transistors in at least one of the plurality of basic cells having a gate length different from that of the one or more transistors in the other basic cell.
In the semiconductor integrated circuit device, the one or more transistors in at least one of the basic cells has a gate length different from that of the one or more transistors in the other basic cell, thereby making it possible to select the basic cells depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density using the basic cell having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations using the basic cell having a large gate length.
As a result, it is possible to achieve low power consumption while achieving high speed and high integration density as a whole, and prevent the yield and the performance from being reduced by process variations.
Each of the plurality of the basic cells may include a plurality of the transistors arranged such that they can be selectively combined with each other, and the plurality of transistors in at least one of the plurality of basic cells may have a gate length different from that of the plurality of transistors in the other basic cell.
In this case, the plurality of transistors in at least one of the basic cells has a gate length different from that of the plurality of transistors in the other basic cell, thereby making it possible to select the basic cells depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density using the basic cell having a small gate length, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations using the basic cell having a large gate length.
As a result, it is possible to achieve low power consumption while achieving high speed and high integration density, and prevent the yield and the performance from being reduced by process variations.
At least one of the plurality of transistors may have a gate length different from that of the other transistors in each of the basic cells.
In this case, the transistors can be selected depending on the necessity of operating at high speed, the necessity of reducing power consumption, and the necessity of design precision in each of the basic cells. Consequently, it is possible to construct a circuit which is operable at high speed and can be increased in integration density by connecting the transistors having a small gate length in each of the basic cells, and construct a circuit which can be reduced in power consumption and is hardly affected by process variations by connecting the transistors having a large gate length.
As a result, it is possible to achieve low power consumption while achieving high speed and high integration density for each of the basic cells as a whole, and prevent the yield and the performance from being reduced by process variations.
At least one of the plurality of transistors may be arranged in a direction different from the direction in which the other transistors are arranged in each of the basic cells.
In this case, at least one of the transistors is arranged in the direction differ
Ogura Isao
Ueda Yoshitaka
Armstrong Westerman & Hattori, LLP
Lee Eddie
Sanyo Electric Co,. Ltd.
Warren Matthew E.
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