Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-12-26
2003-10-07
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S056000, C361S111000, C257S174000, C257S355000
Reexamination Certificate
active
06631061
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor integrated devices and, more particularly, to a semiconductor integrated device having a plurality of circuit blocks that respectively use a plurality of power supply sources.
2. Description of Related Art
In general, in a semiconductor integrated device including a plurality of circuit blocks, a power supply and a ground (ground potential) in each of the circuit blocks are isolated from each other to prevent noises generated in one of the circuit blocks from propagating to another circuit block.
FIG. 6
shows an equivalent circuit of the semiconductor integrated device.
The semiconductor integrated device shown in
FIG. 6
includes three circuit blocks
1
,
2
and
3
. The circuit block
1
connects to a power supply terminal V
DD
1
and a ground terminal GND
1
. The circuit block
2
connects to a power supply terminal V
DD
2
and a ground terminal GND
2
. The circuit block
3
connects to a power supply terminal V
DD
3
and a ground terminal GND
3
. A signal circuit between the circuit blocks
1
and
2
is connected by a signal interface S
12
. A signal circuit between the circuit blocks
2
and
3
is connected by a signal interface S
23
. The device has a structure in which the power supply and the grounding of the circuit blocks
1
through
3
are separated by metal wirings. Therefore, it is difficult with this structure for noises generated in one of the circuit blocks to propagate to another circuit block.
A high resistance of a semiconductor substrate exists between the grounds of the circuit blocks
1
-
3
. Therefore, the semiconductor integrated device has a structure equivalent to the one shown in
FIG. 6
in which substrate resistor R
12
and R
23
, each having a high resistance value are connected between the grounds.
SUMMARY OF THE INVENTION
In the semiconductor integrated device shown in
FIG. 6
, for example, when electrostatic discharge of a high voltage is applied between the ground terminal GND
1
of the circuit block
1
and the power supply terminal V
DD
2
of the circuit block
2
, a high voltage is applied to both ends of the signal interface S
12
that connects the circuit blocks
1
and
2
, due to the presence of the substrate resistor R
12
of a high resistance value in a discharge route. As a result, a dielectric breakdown likely occurs, and a sufficient dielectric strength against electrostatic discharge is not attained.
Japanese patent No. HEI 6-93497 describes a complementary MIS integrated circuit having a plurality of independent circuit blocks, and bi-directional P-N junction diodes provided between power supply terminals and ground/power supply terminals of each of the respective circuit blocks, to thereby form discharge routes having a lower impedance than that of the substrate. However, in this circuit, a current starts flowing in a forward bias when a noise voltage of about 0.7V is applied to the diode. Therefore, the circuit does not provide a sufficient countermeasure against noises.
Japanese Laid-open patent application HEI 2-111046 describes an electrostatic discharge (ESD) protection circuit for a monolithic IC, in which a circuit having diodes in a forward bias and in an reversed bias that are connected in parallel with each other is connected between a plurality of power supply terminals. However, this circuit is aimed at protecting the IC from an abnormal voltage between a power supply terminal and the signal terminal or an abnormal voltage between the power supply terminals, and the circuit of parallel-connected diodes is not connected between the ground terminals. Also, when one power supply voltage is lower than another power supply voltage in a normal operation, a current flows in the diodes, possibly resulting in the damage of the IC or a power supply circuit.
Further, Japanese Laid-open patent application HEI 8-172188 describes a semiconductor device that includes a first protection circuit and a second protection circuit connected between terminals of a monitor transistor to be protected and either a power supply or a grounding. The first protection circuit has a plurality of diodes serially connected in one direction, and the second protection circuit has one or more diodes serially connected in a second direction. However, this publication does not describe a plurality of circuit blocks that respectively have independent power supply terminals and ground terminals.
In view of at least the above, it is an object of the present invention to at least provide a semiconductor integrated device which is provided with sufficient countermeasures against noises and electrostatic discharge.
In accordance with the exemplary embodiments of the present invention, a plurality of diodes are connected between ground terminals of a plurality of circuit blocks that are included in a semiconductor integrated device. A noise current does not flow unless a noise voltage that may be applied between the ground terminals exceeds at least a forward bias voltage of two of the diodes. On the other hand, when electrostatic discharge having a high voltage is applied between the ground terminals, the voltage is clamped through the plurality of diodes, with the result that the dielectric breakdown of a signal interface or the like is prevented.
In accordance with one exemplary embodiment of the present invention, a semiconductor integrated device may consist of:
N number of circuit blocks (N is an integer that is 2 or greater), each circuit block being connected to a power supply terminal and a ground terminal;
a signal interface unit that connects signal circuits among the N number of circuit blocks;
a plurality of first diodes serially connected to one another in a first direction between the ground terminal of a first one of the N number of circuit blocks and the ground terminal of a K-th one of the N number of circuit blocks (K=2, 3, . . . , N); and
a plurality of second diodes serially connected to one another in a second direction that is opposite to the first direction between the ground terminal of the first circuit block and the ground terminal of the K-th circuit block.
In accordance with a second exemplary embodiment of the present invention, a semiconductor integrated device may consist of:
N number of circuit blocks (N is an integer that is 2 or greater), each circuit block being connected to a power supply terminal and a ground terminal;
a signal interface unit that connects signal circuits among the N number of circuit blocks;
a plurality of first diodes serially connected to one another in a first direction between the ground terminal of a K-th one of the N number of circuit blocks and the ground terminal of a (K+1)-th one of the N number of circuit blocks (K=1, 2, 3, . . . , N−1); and
a plurality of second diodes serially connected to one another in a second direction that is opposite to the first direction between the ground terminal of the K-th circuit block and the ground terminal of the (K+1)-th circuit block.
Preferably, each of the N number of circuit blocks may have one diode or a plurality of serially connected diodes, each having a cathode connected to the power supply terminal and an anode connected to the ground terminal,
Further, each of the N number of circuit blocks may further include a bipolar transistor having an emitter and a collector connected between the power supply terminal and the ground terminal and a base connected to one of the power supply terminal and the ground terminal through a Zener diode and connected to the other through a resistor.
In the semiconductor integrated device described above, the plurality of first diodes may include a diode having an anode electrode that is connected to a P
+
layer formed in a P well of the semiconductor integrated device and a cathode electrode that is connected to an N
+
layer formed in the P well. Also, the plurality of second diodes may include a diode having an anode electrode that is connected to a P
+
layer formed
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