Static information storage and retrieval – Powering
Reexamination Certificate
2001-03-01
2002-05-07
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Powering
C361S056000
Reexamination Certificate
active
06385116
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor integrated device, especially to the semiconductor integrated device including the function of effectively preventing the electrostatic destruction (hereinafter referred to as “ESD”) of an integrated circuit by suitably configuring a protective circuit against static electricity.
(b) Description of the Related Art
The development of the fine processing technology promotes the higher integration and the higher speed of the semiconductor integrated circuit. The progress of the miniaturization reduces the resistance of the element to the static electricity. In the conventional semiconductor integrated circuit, protective diodes are connected in a reverse direction between a signal terminal and a power source line and between a signal terminal and a ground line to bypass the electrostatic energy to the power source line and the ground line, thereby protecting the internal circuit from the ESD. However, in the thus configured protective circuit, the sufficient protection cannot be achieved when either of the power source line and the ground line is open. Several semiconductor integrated circuits have been proposed to meet the sufficient protection of the circuit.
As shown in
FIG. 1
, a conventional semiconductor integrated circuit described in JP-A-11(1999)-74468 includes a PNP protective transistor Q
11
and an NPN protective transistor Q
12
connected to signal terminals for protecting a circuit
11
to be protected from static electricity. The emitter, the collector and the base of the protective transistor Q
11
are connected to the signal terminal
15
, a ground line
14
and a power source line
13
, respectively. The emitter, the collector and the base of the protective transistor Q
12
are connected to the signal terminal
15
, the power source line
13
and the ground line
14
, respectively. A pair of protective diodes D
11
and D
12
are parasitic diodes positioned between the bases and the emitters of the protective transistors Q
11
and Q
12
, respectively.
When the power source line is closed and the signal terminal
15
receives a positive electric surge, or the ground line is closed and the signal terminal
15
receives a negative electric surge, the internal circuit is protected by the forward directed conduction of the base-emitter junction of the protective transistor. On the other hand, when the power source line is closed and the signal terminal
15
receives a negative electric surge, and when the ground line is closed and the signal terminal
15
receives a positive electric surge, the internal circuit is protected by the instantaneous transistor operation, or a surge charge is discharged to the power source line or the ground line by the larger current flowing in the collector when a smaller surge current flows in the base.
In accordance with the technique described in the above publication, the internal circuit can be effectively protected when one of the power source line and the ground line is open.
However, the ESD may take place in a variety of ranges from the manufacture to the application of the semiconductor integrated circuit, and the reasons of the occurrence thereof are not necessarily the positive or negative surge voltage applied to the signal terminals. In the protective circuit against the ESD (hereinafter referred to as “ESD protective circuit”) described in the above publication, when a circuit to be protected is, for example, a common-emitter differential amplifier having a pair of differential transistors, and a power source line and a ground line both of which are open, at least one of the differential pair transistors is always subjected to reverse breakdown and destroyed by a surge voltage applied between the differential input and output.
Accordingly, the ESD protective circuit must be mounted such that the semiconductor integrated circuit in any conduction state is effectively protected if the surge voltage is applied between any two of the terminals.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a semiconductor integrated device which can be effectively protected from a charge between any two of terminals of the semiconductor integrated device having any conduction state.
Thus, the present invention provides a semiconductor integrated device including: a ground line; a power source line having a higher potential than that of the ground line; a functional circuit connected between the ground line and the power source line and having a plurality of signal terminals; and an ESD protective circuit for protecting the functional circuit, the ESD protective circuit including a pair of protective diodes each connected in a reverse direction between each of the signal terminals and one of the power source line and the ground line, a bipolar transistor having a current path connected between the power source line and the ground line, and a capacitor connected between a collector and a base of the bipolar transistor.
In accordance with the present invention, the protection against the ESD effectively functions regardless of the operation conditions and the circumstances of the connection of the terminals because the bipolar transistor and the capacitor form a current path for flowing discharge current.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 5144519 (1992-09-01), Chang
patent: 5631793 (1997-05-01), Ker et al.
patent: 5654862 (1997-08-01), Worley et al.
patent: 5717560 (1998-02-01), Doyle et al.
patent: 5818086 (1998-10-01), Lin et al.
patent: 5940258 (1999-08-01), Duvvury
patent: 5986862 (1999-11-01), Kim
patent: 5990723 (1999-11-01), Tanase
patent: 6144542 (2000-11-01), Ker et al.
patent: 11-74468 (1999-03-01), None
Le Vu A.
Phung Anh
Rosenman & Colin LLP
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