Semiconductor integrated circuits and manufacturing process ther

Details Semiconductor integrated circuits and manufacturing process ther Semiconductor integrated circuits and manufacturing process ther

1984-11-09

1985-09-24

Edlow, Martin H.

357 42, 357 41, 357 55, 357 56, 357 71, 357 49, H01L 2702, H01L 2906

Patent

active

045435928

ABSTRACT:
A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.

REFERENCES:
patent: 3593068 (1971-07-01), Rosier
patent: 3751292 (1973-08-01), Kongable
patent: 3838442 (1974-09-01), Humphreys
patent: 3861968 (1975-01-01), Magdo
patent: 4191595 (1980-03-01), Aomura
James, R. P., "Complementary Metal-Oxide Semiconductor Device", IBM Tech. Discl. Bull., vol. 16, No. 6, p. 1998, Nov. 1973.
Lee, C. H., "Bipolar Transistor Fabrication Process", IBM Tech. Discl. Bull., vol. 20, No. 5, pp. 1753-1754, Oct. 1977.

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