Semiconductor integrated circuit with reduced power consumption

Details Semiconductor integrated circuit with reduced power consumption Semiconductor integrated circuit with reduced power consumption

1988-05-05

1990-01-30

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307491, 307443, 307455, H03K 1716, H03K 19086

Patent

active

048975605

ABSTRACT:
A semiconductor integrated circuit includes a logic circuit which has first and second transistors constituting an emitter coupled transistor pair and a third transistor which is used as a constant current source, a bias circuit which includes a fourth transistor having an emitter from which a first predetermined voltage is supplied to a base of the third transistor and an impedance having one end coupled to a first power source and another end coupled to a base of the fourth transistor to supply a second predetermined voltage thereto, and a clamping circuit. The clamping circuit is OFF and does not perform a clamping operation with respect to the base of the fourth transistor when the entire semiconductor integrated circuit needs to operate. When the entire semiconductor integrated circuit does not need to operate, the clamping circuit is ON to clamp the base potential of the fourth transistor so as to reduce the power consumption of the semiconductor integrate circuit.

REFERENCES:
patent: 3794861 (1974-02-01), Bernacchi
patent: 4490670 (1984-12-01), Wong
patent: 4533842 (1985-08-01), Yang et al.
patent: 4599521 (1986-07-01), Kanai et al.
patent: 4625129 (1986-11-01), Ueno
patent: 4678935 (1987-07-01), Nawata et al.

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