Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-12-20
2002-05-28
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06396319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a differential amplification circuit.
2. Description of the Background Art
In the case of amplifying signals of various sensors, a differential amplification circuit is often used. Depending on the use, the circuit is requested to operate normal from immediately after power is turned on. When a differential amplification circuit takes the form of a C-coupled application circuit having a large time constant (&tgr;), the request is addressed by, for example, separately adding a quick charging circuit as disclosed in Japanese Unexamined Patent Application No. 6-104660.
FIG. 7
is a circuit diagram showing a conventional differential amplification circuit having a quick charging/discharging circuit. In
FIG. 7
, a terminal P
0
for receiving an input signal from an ac signal source SIG
1
is connected to a terminal P
1
via a capacitor C
2
. The terminal P
1
is connected to one end of a resistor R
24
. The other end of the resistor R
24
is connected to one of electrodes of a capacitor C
3
, one end of a resistor R
25
, and an input of a buffer BF
1
. The other end of the resistor R
25
is connected to one end of a resistor R
26
and a positive electrode of a reference voltage source
31
. The other end of the resistor R
26
is connected to an input of a buffer BF
2
, and the other electrode of the capacitor C
3
is connected to the ground. The reference voltage source
31
generates a reference voltage VREF
1
from its positive electrode, and its negative electrode is connected to the ground.
An inversion input of an operational amplifier OP
2
receives an output of the buffer BF
1
via a resistor R
22
, and a non-inversion input of the operational amplifier OP
2
receives an output of the buffer BF
2
via a resistor R
23
and is connected to the positive electrode of the reference voltage source
31
via a resistor R
27
. The buffers BF
1
and BF
2
are disposed at the inversion input and non-inversion input of the operational amplifier OP
2
, respectively, in consideration of the fact that the input impedance of the operational amplifier OP
2
is not high from a viewpoint of the configuration of the circuit.
An output of the operational amplifier OP
2
is connected to an output terminal P
2
and is fed back to the inversion input via a resistor RFB. The differential amplifier part is constructed by the ac signal source SIG
1
, capacitors C
2
and C
3
, resistors R
22
to R
27
and RFB, reference voltage source
31
, operational amplifier OP
2
, and buffers BF
1
and BF
2
.
An LPF (Low Pass Filter) is constructed by the capacitor C
3
and a balance resistor R
24
in an input buffer unit
6
. An HPF (High Pass Filter) is constructed by the capacitor C
2
and a synthetic resistor of the balance resistor R
24
and a resistor R
25
. By the combination of the LPF and the HPF, a kind of BPF (band pass filter) is obtained. The resistor R
26
is provided to compensate an error corresponding to an amount of a bias current in the input part of the buffer BF
1
caused by the resistor R
25
. The resistor R
26
is set to have the same resistance value as that of the resistor R
25
.
The resistors R
24
, R
25
, and R
26
in the input buffer unit
6
are set to, for example, 5 K&OHgr;, 800 K&OHgr;, and 800 K&OHgr;, respectively. The capacitor C
2
is set to 1 &mgr;F and the capacitor C
3
is set to 5 pF.
A quick charging/discharging circuit
5
is connected to the terminal P
1
. The quick charging/discharging circuit
5
has an operational amplifier OP
1
, an NPN bipolar transistor Q
5
, a capacitor C
11
, and resistors R
11
and RPD. The capacitor C
11
and the resistors R
11
and RPD are connected in series between a power source voltage Vcc and a ground level. The base of the NPN bipolar transistor Q
5
is connected to a node N
11
which is positioned between the resistors R
11
and RPD.
The terminal P
1
is connected to the inversion input of the operational amplifier OP
1
. The positive electrode of a reference voltage source
32
is connected to the non-inversion input of the operational amplifier OP
1
. An output of the operational amplifier OP
1
is connected to the terminal P
1
and is fed back to the non-inversion input. The reference voltage source
32
generates a reference voltage VREF
2
from its positive electrode, and its negative electrode is connected to the ground. The reference voltage VREF
2
of the reference voltage source
32
is a voltage desired to quickly rise immediately after turn-on of power. The reference voltage VREF
2
is set to, for example, the same voltage as the reference voltage VREF
1
.
As each of the reference voltage sources
31
and
32
, for example, a band gap circuit for generating the reference voltage VREF
1
or VREF
2
on the basis of the power source voltage Vcc is used. The band gap circuit can generate the reference voltage VREF
1
or VREF
2
which can rise to a stable voltage almost equal to the power source voltage Vcc.
The emitter of the NPN bipolar transistor Q
5
is connected to the ground, and the collector is connected to the operational amplifier OP
1
. Consequently, the NPN bipolar transistor Q
5
functions as a drive current source of the operational amplifier OP
1
. When the NPN bipolar transistor Q
5
is in an ON state, the operational amplifier OP
1
is in an enable (operable) state. When the NPN bipolar transistor Q
5
is in an OFF state, the operational amplifier OP
1
is in a disable (inoperative) state.
The differential amplification circuit having such a configuration executes a differential amplification operation by the operational amplifier OP
2
on the basis of an ac signal obtained from the ac signal source SIG
1
. In the operation, the ac signal is supplied via the capacitor C
2
to the terminal P
1
. When the capacitance value of the capacitor C
2
and the resistance value of the resistor R
25
are large, however, it takes time for the potential of the terminal P
1
to follow the potential of the terminal P
0
. It is therefore difficult to normally perform the differential amplifying operation from immediately after turn-on of power because a current for charging/discharging the capacitor C
2
passes through the resistor R
25
.
The quick charging/discharging circuit
5
is added to solve the problem and is designed so that the potential of the terminal P
1
exceeds a potential VBE (0.6 to 0.7V) between the base and emitter of the NPN bipolar transistor Q
5
at the node N
11
only for a predetermined period immediately after turn-on of power by the capacitor C
11
and the resistors R
11
and RPD.
The NPN bipolar transistor Q
5
therefore enters an ON state for a predetermined period immediately after turn-on of power to thereby make the operational amplifier OP
1
enter an enable state. By the output of the operational amplifier OP
1
, the terminal P
1
is rapidly charged or discharged to the reference voltage VREF
2
.
After that, when the NPN bipolar transistor Q
5
enters an OFF state, the operational amplifier OP
1
enters a disenable state and the output of the operational amplifier OP
1
becomes a high impedance. The quick charging/discharging operation by the quick charging/discharging circuit
5
is finished.
As described above, the quick charging/discharging circuit
5
executes the charging/discharging operation to make the terminal P
1
rapidly have the reference voltage VREF
2
in the predetermined period immediately after turn-on of power. Consequently, the differential amplification circuit can normally perform the differential amplification operation from immediately after turn-on of power.
The conventional differential amplification circuit having the quick charging/discharging circuit is constructed as described above. The quick charging/discharging circuit is constructed by using the operational amplifier. The operational amplifier has to have therein a capacitor for phase compensation and the like, so that it is a circuit device unsuitable for reduction in chip size. It caus
Cunningham Terry D.
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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