Semiconductor integrated circuit with pulsed clock data latch

Details Semiconductor integrated circuit with pulsed clock data latch Semiconductor integrated circuit with pulsed clock data latch

2006-06-28

2008-10-28

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S199000

Reexamination Certificate

active

07443218

ABSTRACT:
A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.

REFERENCES:
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patent: 2000-232339 (2000-08-01), None
patent: 2004-56667 (2004-02-01), None
T. Kitahara et al., “A Clock-Gating Method for Low-Power LSI Design,” Proceedings of the ASC-DAC '98 Conference, 1998, pp. 307-312.
M. Hamada et al., “A Conditional Clocking Flip-Flop for Low Power H. 264/MPEG-4 Audio/Visual Codec LSI,” IEEE 2005 Custom Integrated Circuits Conference, 2005, pp. 527-530.
Y. Ueda et al., “6.33mw MPEG Audio Decoding on a Multimedia Processor,” 2006 IEEE International Solid-State Circuits Conference, Session 22, Low Power Media, 22.7, Feb. 8, 2006, pp. 414-415.

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