Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1998-09-09
2001-02-20
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S333000
Reexamination Certificate
active
06191633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a semiconductor integrated circuit which may possibly be destroyed by electrostatic discharge and particularly, to a semiconductor integrated circuit provided with metal insulator semiconductor (MIS) transistor as a transfer gate.
2. Description of the Prior Art
Generally, the breakdown of semiconductor integrated circuits by electrostatic discharge is of great interest, as the scale of integrated circuits becomes greater. Consequently, various models such as human model, charged device model and charged package model are used to analyze the electrostatic breakdown of integrated circuits. It is desirable that the integrated circuits do not suffer the electrostatic breakdown under each model. Particularly, the integrated circuit is usually required to be resistant electrostatically against around 600 Volt under the charged device model and the charged package model.
For preventing the electrostatic discharge, there is disclosed in Japanese Patent 07169962A (1985) a semiconductor circuit with protection MOSFETs connected between a external terminal and a gate of an output MOSFET, wherein the channel length of the protection MOSFETs are greater than or equal to that of the output MOSFET.
A suitable voltage source is connected with the gates of the protection MOSFETs to turn off the protection MOSFETs during the normal state. If an abnormally high voltage is applied to the protection MOSFETs, the protection MOSFETs are turned on to prevent the breakdown of the oxide film of the output MOSFET.
There is also disclosed in Japanese Patent 63-181469A (1988) another protection circuit, wherein a protection MOS FET is placed in between the gate and the source of an input MOS transistor. This protection circuit prevents the electrostatic breakdown of the insulating film of the input MOS transistor, when a surge voltage is inputted into the input MOS transistor.
The recent high speed DRAMs are often provided with a transfer gate made of MIS transistor between an input pad and an internal circuit, wherein the gate of the MIS transistor is connected with a voltage source with its drain being connected with the internal circuit and with its source being connected through a register with an input pad or external terminal, and a protection element such as diode is inserted between the input pad and the ground, whereby the breakdown by the electrostatic dischargeis prevented.
The above-mentioned transfer gate is used to limit the amplitude of external signals and to adapt the timing of the external signals with that of the internal circuit.
However, in Reference 1, the number of the protection MOSFETs increases, as the number of the output transistors which should be protected increases. Therefore, the conventional circuit as disclosed in the above-mentioned reference has a disadvantage that the construction of the circuit becomes complex and the integration degree can not be improved. Further, the circuit construction becomes more complex, so as to prevent the breakdown of the protection MOSFET itself. In reference 2, the protection MOS FET itself breaks down under severe conditions.
Further, in case of semiconductor integrated circuits such as DRAM which is provided with a transfer gate for each input pad, the inventors of the present invention found that the gate insulating film of the MIS transistor used as the transfer gate is easily broken down under the electrostatic discharge, when the gradually charged electric charges are abruptly discharged during an experiment on the basis of the charged device model. The fact is that the breakdown could not be prevented even by inserting any protection element between the input pad and the ground.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a protection element with a high resisting voltage required in the charged device model experiment.
Another object of the present invention is to provide a clamping element which can suppress the decline of the integration degree at a minimum.
A further object of the present invention is to provide a semiconductor integrated circuit having transfer gates with a protection element for preventing the breakdown of insulating film.
In accordance with the present invention, there is provided a parasitic bipolar transistor as a clamping element to prevent the breakdown of a semiconductor integrated circuit.
Further, according to the present invention, there is provided a semiconductor integrated circuit which comprises an input pad and an internal circuit, wherein a transfer gate is connected between the input pad and the internal circuit. The transfer gate is connected with a clamping element which may be a bipolar transistor, or a MOS transistor whose gate is supplied with thick insulating film.
According to the present invention as explained above, the MIS transistor as a transfer gate connected with a clamping element can be protected against the breakdown.
REFERENCES:
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patent: 4922371 (1990-05-01), Gray et al.
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patent: 5663678 (1997-09-01), Chang
patent: 5760630 (1998-06-01), Okamoto
patent: 5770964 (1998-06-01), Suma
patent: 5942931 (1999-08-01), Yanai
patent: 5973901 (1999-10-01), Narita et al.
patent: 5-667962 (1981-06-01), None
patent: 5-9231847 (1984-12-01), None
patent: 3-234058 (1991-10-01), None
patent: 7-169962 (1995-07-01), None
Fujii Takeo
Horiguchi Yoko
Narita Kaoru
NEC Corporation
Young & Thompson
Zweizig Jeffrey
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