Semiconductor integrated circuit with master and slave latches

Details Semiconductor integrated circuit with master and slave latches Semiconductor integrated circuit with master and slave latches

1990-11-07

1992-11-10

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 3072721, H03K 3289

Patent

active

051626675

ABSTRACT:
A semiconductor integrated circuit of master and slave latches and the like that reduces power consumption by supplying a second clock which is a synchronous with a first clock to a slave latch only when the first clock that determines the latch period is supplied to a master latch, discontinuing the supply of the second clock after the master latch completes its latch action in the case that the supply of the first clock to the master latch is discontinued, and discontinuing the supply of clocks when latch action is not required, to reduce loads connected to them.

REFERENCES:
patent: 4456837 (1984-06-01), Schade, Jr.
patent: 4691122 (1987-09-01), Schnizlein et al.
patent: 4705965 (1987-11-01), Stuyt
patent: 4970407 (1990-11-01), Patchen

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