Semiconductor integrated circuit with layer for isolating elemen

Details Semiconductor integrated circuit with layer for isolating elemen Semiconductor integrated circuit with layer for isolating elemen

1994-10-13

1996-11-26

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

257552, 257551, 257532, 327382, 327482, H01L 2900

Patent

active

055788629

ABSTRACT:
By reverse biasing the PN junction formed around a semiconductor element, the semiconductor element is isolated from other elements. The PN junction around the semiconductor element is a junction between a layer surrounding the semiconductor element and a layer disposed outside the layer. Jointly with the layer constituting the semiconductor, the layer surrounding the semiconductor element forms a parasitic diode. The potential of the layer on the semiconductor element to be connected to the layer surrounding the semiconductor element is detected, and based on this potential, the voltage to be applied to the parasitic diode is controlled so as to be constant. When the voltage to be applied to the parasitic diode is lower than a threshold, the parasitic diode will be in a cutoff state.

REFERENCES:
patent: 4935796 (1990-06-01), Zuffada et al.
patent: 4979008 (1990-12-01), Siligoni et al.
patent: 5051612 (1991-09-01), Agiman
patent: 5179432 (1993-01-01), Husher
Revised Edition: Integrated Circuit Engineering (1) to Hisayoshi Yanai et al, published by Corona Publishing Co., Ltd., Apr. 30, 1987.
Toshiba Review, vol. 37, No. 13, 1982, pp. 1153-1158.

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