Semiconductor integrated circuit with improved I/O structure wit

Details Semiconductor integrated circuit with improved I/O structure wit Semiconductor integrated circuit with improved I/O structure wit

1990-04-20

1992-03-31

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072966, H03K 19092, H03K 301

Patent

active

051011255

ABSTRACT:
A semiconductor integrated circuit includes a bias voltage generating circuit and first- and second-level signal generating circuits. The bias voltage generating circuit includes a bandgap reference circuit for generating a first fixed voltage as a first bias voltage and a second fixed voltage. A second bias voltage is generated on the basis of the second fixed voltage. The second-level signal generating circuit receives a predetermined first-level signal and generates a predetermined second-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit. The first-level signal generating circuit receives the predetermined second-level signal and generates the predetermined first-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit.

REFERENCES:
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4785205 (1988-11-01), Sanwo et al.
patent: 4794317 (1988-12-01), van Tran
patent: 4806799 (1989-02-01), Pelley, III et al.
patent: 4841175 (1989-06-01), DeMan et al.
patent: 4891535 (1990-01-01), Etheridge
patent: 4947061 (1990-08-01), Metz et al.
patent: 4968905 (1990-11-01), Sanwo et al.
"Fabrication and Evaluation of The ECL/TTL Compatible Bi-CMOS Gate Array", T. IEE Japan, vol. 108-C, No. 12, 1988, Y. Sugimoto and H. Hara, et al.

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