Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-06-05
2004-05-18
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S566000
Reexamination Certificate
active
06737910
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2002-172770 filed on Jun. 13, 2002, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit which is provided with a built-in DC—DC regulator.
2. Description of the Related Art
Semiconductor integrated circuits in recent years tend to use a reduced power supply voltage to drive internal circuitry due to an increasing degree of finer fabrication and higher circuit density. To this end, a DC—DC regulator is provided inside devices for the purpose of reducing an externally provided power supply voltage to generate an internal power supply voltage. This internal power supply voltage is supplied to each circuit part inside the integrated circuit.
FIG. 1
is an illustrative drawing showing a structure relating to the supply of a power-supply voltage in a related-art semiconductor integrated circuit.
In the semiconductor integrated circuit of
FIG. 1
, an external power supply voltage VCC applied to a power-supply input terminal
11
is led to a DC—DC regulator
12
. The DC—DC regulator
12
generates an internal power supply voltage by reducing the external power supply voltage VCC, and transmits the internal power supply voltage to power supply lines
13
. The power supply lines
13
are laid out to reach each corner of the semiconductor integrated circuit in order to supply the internal power supply voltage to each interior circuit
15
. Further, the power supply lines
13
are connected to a terminal
14
to which a condenser is to be coupled for the purpose of suppressing oscillation. A ground voltage VSS is supplied to ground terminals
16
from the exterior, and is supplied to each circuit unit inside the semiconductor integrated circuit.
FIG. 2
is an illustrative drawing for explaining an operation of the mechanism as shown in
FIG. 1
that supplies a power supply voltage.
In
FIG. 2
, an external power supply voltage is denoted as V1, and an internal power supply voltage is designated as V2. The DC—DC regulator
12
receives the external power supply voltage V1, and reduces it to generate the internal power supply voltage V2. The internal power supply voltage V2 is transmitted to the power supply line
13
. The power supply line
13
extends a long distance, so that a potential drop as shown in the upper half of
FIG. 2
is observed. In the upper half of
FIG. 2
, the horizontal axis represents the extension of the line, and the vertical axis represents the power supply voltage.
A drop in the power supply voltage caused by line resistance inside semiconductor integrated circuits has been recognized as a cause of circuit malfunction. In order to obviate this problem, software may be used to estimate electric current running through the power supply lines, and the power supply lines may be widened through optimization based on the software analysis. This method, however, offers only a limited effect of voltage-drop reduction. As a different measure, regulators may be provided for respective circuit modules that consume power supply, thereby stabilizing a power supply voltage at each of the circuit modules. Since a power supply circuit occupies a relatively large area inside semiconductor integrated circuits, this method is not practical from an economic standpoint. It is conceivable to adopt a circuit design that provides a voltage margin by taking into account a power supply voltage drop. This is not desirable because such a design puts a limit on performance. Since a power supply voltage of recent semiconductor integrated circuits has been lowered significantly, a tolerable range of an internal power supply voltage is now quite narrow. As a result, it is becoming increasingly difficult to cope with this issue through simple design modification.
Accordingly, there is a need for a semiconductor integrated circuit which can prevent a drop in an internal power supply voltage generated by a DC—DC regulator without increasing chip size.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor integrated circuit that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor integrated circuit particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a semiconductor integrated circuit, including a first power supply line which supplies an external power supply voltage provided from an exterior of the circuit, a second power supply line which supply an internal power supply voltage to an interior circuit, a plurality of NMOS transistors which are situated at different locations, and have drain nodes thereof coupled to the first power supply line and source nodes thereof coupled to the second power supply line, and a regulator circuit which supplies a reference voltage to gate nodes of the plurality of NMOS transistors.
In the semiconductor integrated circuit as described above, a voltage drop may be generated by line resistance along the first power supply line when it extends a long distance. Even if this is the case, the NMOS transistors receiving the reference voltage at their gate nodes generate the internal power supply voltage at their source nodes based on the external power supply voltage. The internal power supply voltage is thus lower than the reference voltage by the threshold voltage of the NMOS transistors. In this manner, the semiconductor integrated circuit of the present invention can maintain a constant internal power supply voltage on the second power supply line at any given locations.
The regulator serves only to apply the reference voltage to the gates of the NMOS transistors, and almost no current flows from the regulator the gate of each NMOS transistor. Even if lines extend a long distance from the regulator to the gates of the NMOS transistors, therefore, almost no voltage drop occurs along the lines.
In the construction as described above, the NMOS transistors can be regarded as transistors for supplying outputs that are generally provided at the outputting part of a DC—DC regulator. One way to look at the present invention is that the regulator has a plurality of power supply points, which are distributed at various locations, and that these power supply points distributed at various locations in the semiconductor integrated circuit can control voltages even when the external power supply voltage is lowered due to line resistance, thereby achieving a predetermined voltage level.
The number of the power supply points may be increased if necessary. It is thus possible to supply a stable power supply voltage to circuits that consume a large amount of electric currents, without resorting to the use of widened power supply lines. When the output transistors of a DC—DC regulator are distributed to various points along the power supply tree, distances between the power supply points and the locations of actual power consumption tend to be short. Further, the provision of more than one power supply point results in a reduced amount of an electric current per power supply point. It is thus possible to suppress a voltage drop to a minimum level when it is cause
Fujii Hiroshi
Isawa Shoji
Kitagawa Yasuhiro
Yaguchi Yukihiro
Arent & Fox PLLC
Fujitsu Limited
Zweizig Jeffrey
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