Semiconductor integrated circuit testing system and method

Details Semiconductor integrated circuit testing system and method Semiconductor integrated circuit testing system and method

2001-09-28

2004-08-31

Pert, Evan (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090, C324S1540PB

Reexamination Certificate

active

06784681

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit testing method in which electric characteristics of a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer are tested in the lump at wafer level, and a testing system used in the testing method.
Conventionally, a semiconductor chip is electrically connected to a lead frame through bonding wires and the semiconductor chip and inner leads of the lead frame are sealed in a resin or ceramic, so as to be mounted on a printed substrate as a semiconductor device.
However, owing to demands for compactness and price reduction of electric equipment, a method for mounting, on a circuit substrate, a semiconductor chip (semiconductor integrated circuit device) in a bare-chip state cut out from a semiconductor wafer has been developed, and it is desired to supply a bare-chip with assured quality at a low price. In order to assure the quality of a bare-chip, it is preferred from the viewpoint of cost reduction to carry out a burn-in test on a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer in the lump.
Therefore, a semiconductor integrated circuit testing system for testing electric characteristics of a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer in the lump at wafer level by using a testing substrate having probe terminals disposed in positions respectively corresponding to external electrodes of the plural semiconductor integrated circuit devices has been proposed.
FIG. 7
shows the cross-sectional structure of the conventional semiconductor integrated circuit testing system. A large number of external electrodes
2
are provided on a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer
1
, and the periphery of each external electrode
2
is covered with a passivation film
3
.
A testing substrate
4
is provided so as to face the semiconductor wafer
1
. The testing substrate
4
includes an interconnect substrate
5
having interconnect layers
5
a;
an elastic sheet
7
of, for example, a polyimide resin fixed on the interconnect substrate
5
at its periphery with a rigid ring
6
; semispherical bumps
8
provided on the elastic sheet
7
in positions corresponding to the external electrodes
2
of the semiconductor wafer
1
; isolated patterns
9
of, for example, a copper film, integrated with the bumps
8
and provided on the face of the elastic sheet
7
other than the face where the bumps
8
are provided; and an anisotropic conducting rubber sheet
10
provided between the interconnect substrate
5
and the elastic sheet
7
for electrically connecting one end of each interconnect layer
5
a
of the interconnect substrate
5
to the corresponding isolated pattern
9
. The anisotropic conducting rubber sheet
10
has conducting particles
10
a
linearly arranged therein, so that one end of the interconnect layer
5
a
can be electrically connected to the isolated pattern
9
through the conducting particles
10
a.
Also, the other end of the interconnect layer
5
a
of the interconnect substrate
5
is connected to a burn-in system not shown for supplying a power voltage, a ground voltage or a testing voltage such as a signal voltage.
A wafer tray
11
has a wafer holder
11
a
for holding the semiconductor wafer
1
, and the wafer holder
11
a
is provided at its periphery with a ring-shaped sealing member
12
of en elastic substance having a lip-shaped cross-section. A ring-shaped pressure reducing groove
13
is formed on the wafer tray
11
between the wafer holder
11
a
and the sealing member
12
, and opposing portions of the pressure reducing groove
13
are mutually communicated through a communicating path
14
formed below the wafer holder
11
a.
A passage closing valve
15
is provided on one side of the wafer tray
11
, and the passage closing valve
15
is connected to a vacuum pump
17
through a pressure reducing tube
16
.
Now, the method for testing electric characteristics of the plural semiconductor integrated circuit devices formed on the semiconductor wafer
1
by using the semiconductor integrated circuit testing system having the aforementioned structure will be described.
First, the wafer tray
11
is brought close to the testing substrate
4
with the external electrodes
2
of the semiconductor wafer
1
facing the bumps
8
of the testing substrate
4
, so that the wafer tray
11
, the ring-shaped sealing member
12
and the testing substrate
4
can together form a sealed space
18
.
Next, the internal pressure of the pressure reducing groove
13
is reduced by driving the vacuum pump
17
. In this manner, the pressure within the sealed space
18
is reduced, and hence, the cross-sectional shape of the ring-shaped sealing member
12
is elastically deformed to an arch shape. As a result, the testing substrate
4
and the wafer tray
11
are brought further closer to each other, so that the bumps
8
can be definitely brought into contact with the corresponding external electrodes
2
.
Under this condition, a testing voltage is applied from the burn-in system not shown to some of the external electrodes
2
through the interconnect layers
5
a
of the interconnect substrate
5
, the conducting particles
10
a
of the anisotropic conducting rubber sheet
10
, the isolated patterns
9
and the bumps
8
, and output signals output from other of the external electrodes
2
are input to the burn-in system. Thus, the burn-in system can evaluate the electric characteristics of the semiconductor integrated circuit devices.
When the internal pressure of the sealed space
18
is reduced as described above, the testing substrate
4
and the wafer tray
11
are brought close to each other so as to definitely bring the bumps
8
into contact with the corresponding external electrodes
2
. However, at the same time, the interconnect substrate
5
and the wafer tray
11
are also brought close to each other in a region between the ring-shaped sealing member
12
and the bumps
8
positioned in an outermost peripheral region (hereinafter referred to as outermost bumps).
In this case, since the region between the ring-shaped sealing member
12
and the outermost bumps
8
has a comparatively large area, a strong force to bring the interconnect substrate
5
close to the wafer tray
11
works in this region.
However, merely the elasticity of the ring-shaped sealing member
12
having the lip-shaped cross-section works against the force to bring the interconnect substrate
5
close to the wafer tray
11
. Accordingly, in the interconnect substrate
5
having small rigidity as compared with the wafer tray
11
, its periphery is deformed so as to come close to the wafer tray
11
.
Although the rigidity of the interconnect substrate
5
can be increased by increasing the thickness of the interconnect substrate
5
, the weight of the entire testing system is accordingly increased, which is inconvenient for the testing process. Therefore, it is not preferable to increase the thickness of the interconnect substrate
5
.
Accordingly, the bumps
8
positioned in a peripheral region on the elastic sheet
7
(hereinafter referred to as peripheral bumps) are strongly pressed against the corresponding external electrodes
2
while the bumps
8
positioned in a center region on the elastic sheet
7
(hereinafter referred to as center bumps) are weakly pressed against the corresponding external electrodes
2
. Specifically, the force to bring the bumps
8
into contact with the external electrodes
2
is largely varied in the plane of the semiconductor wafer
1
. As a result, the tips of the peripheral bumps
8
are largely deformed, which degrades the durability of the bumps
8
, and the contact resistance between the center bumps
8
and the corresponding external electrodes
2
is disadvantageously increased. Herein, the center region means a large region excluding the peripheral region.
FIG. 8
shows the relationship between the position of

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