Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
2000-07-03
2004-01-27
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
Reexamination Certificate
active
06683336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, a supply method for supplying multiple supply voltages to cells in the semiconductor integrated circuit, and a record medium for storing a supply program of multiple supply voltages in a semiconductor integrated circuit, and more particularly, it relates to the technology capable of integrating the semiconductor integrated circuit with a high density that operates under the multiple supply voltages.
2. Description of the Prior Art
FIG. 15
is a block diagram showing a configuration of a conventional semiconductor integrated circuit. This block diagram shows a part of the conventional semiconductor integrated circuit. In this conventional semiconductor integrated circuit, a plurality of cells
3
are arranged or placed per cell row or per cell column. In each cell row or cell column, a plurality of electrical wires such as an electrical wire
5
for a low supply voltage VDDL, an electrical wire
7
for a high supply voltage VDDH, and an electrical wire for a ground source (not shown) are formed according to demand.
Each cell
3
receives a voltage or voltages from the supply voltage VDDL, or the supply voltage VDDH, or both of them through the electrical wires
5
and
7
in order to perform operation. Accordingly, the conventional semiconductor integrated circuit has the configuration in which the electrical wires
5
and
7
are formed on a cell column even if this cell column requires only one supply voltage.
FIG. 16
is a circuit diagram showing a general configuration of a cell of a level converter (LC) for converting the voltage potential of a signal. In general, this cell of the LC requires multiple supply voltages. The level converter LC shown in
FIG. 16
has an N well region
59
. Two P channel type transistors are formed and connected on the N well region
59
. The drain of each P channel type transistor is connected to each N channel type transistor. Furthermore, both the electrical wire
5
of the low supply voltage VDDL and the electrical wire
7
of the high supply voltage VDDH are formed on the N well region
59
. A power supply section
61
for the N well region
59
is connected to the electrical wire
7
of the high supply voltage VDDH. Thus, the high voltage may be supplied to the N well region
59
through the power supply section
61
.
In the conventional semiconductor integrated circuit, it is required to have the configuration in which a plurality of electrical wires are formed in each cell column in advance or to manually design the electrical wires in order to supply desired supply voltages to a target cell, arranged in the cell column, such as the level converter LC that requires the multiple supply voltages.
However, because it takes long time to manually design the electrical wires and requires a lot of design work for designers, it is difficult to design a large integrated semiconductor chip manually. Furthermore, the area of a cell is increased when a plurality of electrical wires for supply voltages are formed on each cell column, because a width or a diameter of each of the plurality of electrical wires for the supply voltages is larger than that of a normal signal wire for transferring signals. This causes to increase the area of the semiconductor chip of a semiconductor integrated circuit.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional semiconductor integrated circuit, to provide a semiconductor integrated circuit, a supply method for supplying multiple supply voltages in the semiconductor integrated circuit, and a record medium for storing a supply program of multiple supply voltages in the semiconductor integrated circuit that are capable of preventing the increasing of the area of the semiconductor integrated circuit including cells requiring the multiple supply voltages in operation and capable of performing electrical wiring process in the semiconductor integrated circuit.
In accordance with a preferred embodiment of the present invention, a semiconductor integrated circuit comprises a plurality of modules comprising a plurality of cells including first cells operating under a plurality of voltages, and the plurality of cells in the plurality of modules are arranged in a plurality of cell rows or cell columns, and a wiring formed on each cell row or each cell column for supplying one supply voltage in the plurality of voltages, and one supply voltage is supplying to the plurality of cells through the wiring. In the semiconductor integrated circuit, other voltage in the plurality of supply voltages is supplied to each of the first cells through a net for power source supply.
In accordance with another preferred embodiment of the present invention, a semiconductor integrated circuit comprises a plurality of modules comprising a plurality of cells including first cells operating under a plurality of voltages, and the plurality of cells in the plurality of modules are arranged in a plurality of cell rows or cell columns, a first wiring formed on each cell row or each cell column for supplying one supply voltage in the plurality of voltages, and one supply voltage is supplied to each of the first cells in the plurality of cells through the first wiring, and a second wiring for supplying other voltage in the plurality of voltages to each of the first cells through a net for power source supply.
In the semiconductor integrated circuit as another preferred embodiment of the present invention, each first cell operating under the plurality of supply voltages is arranged in a cell row or cell column in which a wiring for supplying a high supply voltage in the plurality of supply voltages is formed.
In the semiconductor integrated circuit as another preferred embodiment of the present invention, each of the first cells to which the plurality of supply voltages are supplied is a level converter.
In the semiconductor integrated circuit as another preferred embodiment of the present invention, the level converter comprise an N well to which one voltage in the plurality of voltages is supplied through the wiring of the power source, a first P channel type MOS transistor formed on the N well and whose source is connected to the wiring, a second P channel type MOS transistor formed on the N well, whose source is connected to the wiring of the power source, whose gate is connected to a drain of the first P channel type MOS transistor, and whose drain is connected to a gate of the P channel type MOS transistor, a third P channel type MOS transistor formed on the N well and whose source is connected to a net for the power source supply, a first N channel type MOS transistor whose source is connected to the drain of the first P channel type MOS transistor, whose gate is connected to the drain of the third P channel MOS transistor, and whose drain is connected to a ground wiring, a second N channel type MOS transistor whose source is connected to the drain of the second P channel type MOS transistor, whose gate is connected to the gate of the P channel type MOS transistor, and whose drain is connected to the ground wiring, and a third N channel type MOS transistor whose source is connected to the drain of the third P channel type MOS transistor, whose gate is connected to the third P channel type MOS transistor, and whose drain is connected to the ground wiring.
In the semiconductor integrated circuit as another preferred embodiment of the present invention, the level converter comprises a first N well to which one voltage in the plurality of voltages is supplied through the wiring of the power source, a second N well to which other voltage in the plurality of voltages is supplied through the net for the power source supply, a first P channel type MOS transistor formed on the first N well and whose source is connected to the wiring, a second P channel type MOS transistor formed on the first N well, whose source is connected to the wiring of the power
Igarashi Mutsunori
Ishikawa Takashi
Kanazawa Masahiro
Mizuno Chiharu
Tanaka Hiroshi
Fahmy Wael
Farahani Dana
Kabushiki Kaisha Toshiba
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