Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-06-03
2001-06-19
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S298000, C327S544000
Reexamination Certificate
active
06249167
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor integrated circuit, a semiconductor device, and electronic equipment comprising the same, and, in particular, to such devices wherein a timekeeper clock signal can be halted by a time measurement circuit.
BACKGROUND ART
A time measurement circuit of this type is shown in
FIG. 12
by way of example. An example of a general-purpose time measurement circuit is shown in FIG.
9
.
FIG. 12
is a block diagram of a prior-art semiconductor integrated circuit comprising a time measurement circuit that operates on an auxiliary clock signal.
The semiconductor integrated circuit comprises a main circuit
710
drive on the basis of a main system clock signal
760
, an auxiliary circuit
730
driven on the basis of an auxiliary clock signal
770
with the objective of providing timing or the like, and an interface circuit
720
that electrically connects together the auxiliary circuit
730
and the main circuit
710
by inter-block signals
781
,
782
, and
783
. In this case, the main system clock signal is a clock for driving the main circuit and the auxiliary clock signal is an assistant clock for providing timing for measuring the passage of time, by way of example,
In addition, the semiconductor integrated circuit comprises a main power supply circuit
750
, which is connected electrically to the main circuit
710
and supplies a potential to the main circuit
710
, and an auxiliary power supply circuit
740
, which is connected electrically to the auxiliary circuit
730
and supplies a potential to the auxiliary circuit
730
.
Within the main circuit
710
are a first control circuit
712
, which receives the main system clock signal
760
and operates in accordance with this main system clock signal
760
, and a second control circuit
714
, which is connected electrically to the first control circuit
712
by an inter-block signal
762
and is connected electrically to the main power supply circuit
750
by the inter-block signal
764
.
Within the auxiliary circuit
730
are a first control circuit
732
, which receives the auxiliary clock signal
770
and operates in accordance with this auxiliary clock signal
770
, a second control circuit
734
connected electrically to the first control circuit
732
by an inter-block signal
772
, and other circuits
736
.
In the semiconductor integrated circuit of the above described configuration, the main system clock signal
760
of the main circuit
710
can be halted by the inter-block signal
764
, independent of the auxiliary circuit
730
.
However, this auxiliary circuit
730
is unable to continue operating independently of the main circuit
710
, nor can the auxiliary clock signal
770
be halted. This leads to a problem in that, although the power consumption of the main circuit can be constrained if necessary, it is not possible to halt the auxiliary circuit and the auxiliary power supply and thus the auxiliary circuit always consumes power, which makes it impossible to reduce the power consumption of the entire semiconductor integrated circuit.
Since the auxiliary clock signal
770
cannot be halted, circuits driven by this clock signal
770
continue to operate regardless of whether or not they are necessary, which increases the power consumption. In particular, if the auxiliary circuit
730
is configured as a time measurement circuit, by way of example, a problem occurs in that a fixed period of time is measured thereby and the auxiliary circuit
730
cannot be halted, even when there is no need to measure time beyond that fixed period, so it is not possible to constrain the power consumption during the time after that fixed period, when there is no longer any need to continue the measurement.
In addition, semiconductor devices with lower voltage specifications are becoming more popular from the viewpoint of reducing the power consumption, and the operation of a time measurement circuit has a large effect on power consumption, even in a semiconductor device which is used together with a time measurement circuit mounted thereon, and thus there are demands for further reductions in power consumption.
The present invention was devised in the light of the above described technical concerns and has the objective of providing a semiconductor integrated circuit, a semiconductor device, and electronic equipment that comprises the same, which are capable of halting the auxiliary circuit when it is not required, to constrain the amount of power consumed by that auxiliary circuit, thus enabling a reduction in the power consumption of the entire semiconductor integrated circuit.
DISCLOSURE OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: at least one first semiconductor circuit operating on the basis of at least one first clock signal; at least one second semiconductor circuit for assisting the first semiconductor circuit, operating on the basis of a request from the first semiconductor circuit and at least one second clock signal independent of the first clock signal. This second semiconductor circuit has halt means that causes the second clock signal to halt.
With a semiconductor integrated circuit having a first semiconductor circuit and a second semiconductor circuit, this aspect of the invention makes it possible for the first semiconductor circuit to halt the operation of the first semiconductor circuit by halting the first clock signal. On the other hand, the operation of the second semiconductor circuit can be halted by halting the second clock signal. In contrast to the prior-art configuration in which it is not possible to halt the second semiconductor circuit, this invention makes it possible to allow the second semiconductor circuit to operate only within a period in which it is used, by halting the second clock signal for a desired period of time, thus reducing the power consumed by the second semiconductor circuit by the amount corresponding to the time in which it is not used.
The halt means may comprise control signal generation means for generating at least one clock control signal for controlling the halting and non-halting of the second clock signal; and operation control means for controlling the halting of operation of the second clock signal, based on the clock control signal.
The halting and non-halting of the second clock signal can be controlled by the operation control means that bases its operation control on the clock control signal. This ensures that the second clock signal can be halted for only the desired period.
The halt means may further comprise: setting means for causing a halt period to be set for the second clock signal, based on a request from the first semiconductor circuit; and counter means for counting the operating period of the second clock signal and outputting the thus-counted counter value to the operation control means. When the counter value has reached the halt period, the operation control means may cause the output of the clock control signal of the control signal generation means, to halt the second clock signal.
A halt start time and halt end time for the halting of the second semiconductor circuit can be set as desired by setting means that is used for setting a halt period for the second clock signal. This makes it possible to control the second semiconductor circuit.
Each of the operation control means, the counter means, and the control signal generation means may be provided with a transistor of a first conductivity type and a transistor of a second conductivity type having a conductivity opposite to the first conductivity type. The transistor of the first conductivity type of the counter means may be electrically disconnected from the transistors of the first conductivity type of the operation control means and the control signal generation means, and the transistor of the second conductivity type of the counter means may be electrically connected to the transistors of the second conductivity type of the operation control means and
Miyayama Yoshiyuki
Oguchi Yasuhiro
Dinh Paul
Oliff & Berridg,e PLC
Seiko Epson Corporation
Wells Kenneth B.
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