Semiconductor integrated circuit protected from element breakdow

Details Semiconductor integrated circuit protected from element breakdow Semiconductor integrated circuit protected from element breakdow

1993-05-26

1994-08-09

Gossage, Glenn

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

365185, 365226, 36523006, 36518909, 307572, 3072964, 3072965, 307584, H03K 17687, G11C 1606

Patent

active

053369521

ABSTRACT:
A semiconductor integrated circuit which is protected from element breakdown includes a memory cell, series-connected first and second program load transistors arranged between the memory cell and the program power source, a boosting circuit for outputting a board voltage higher than the voltage of a program power source, and a controller. The controller applies the boosted voltage to the gates of the first and second program load transistors when program data is set at a first logic level. The controller applies a voltage of about 0 V to the gate of the first program load transistor and an intermediate voltage lower than the voltage of the program power source and higher than 0 V to the gate of the second load transistor when the program data is set at a second logic level.

REFERENCES:
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patent: 4835423 (1989-05-01), de Ferron et al.
patent: 4893275 (1990-01-01), Tanaka et al.
patent: 4916334 (1990-09-01), Minagawa et al.
patent: 4988894 (1991-01-01), Takiba et al.
"A 95ns 256K CMOS EPROM," K. Yoshzaki et al, Digest of Technical Papers, IEEE Solid State Circuits Conference, Feb. 14, 1985, pp. 166-167.

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