Semiconductor integrated circuit package and method of...

Details Semiconductor integrated circuit package and method of... Semiconductor integrated circuit package and method of...

2009-03-13

2010-06-01

Doan, Theresa T (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S106000, C438S124000, C257S666000, C257S676000

Reexamination Certificate

active

07727817

ABSTRACT:
In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits.

REFERENCES:
patent: 6544816 (2003-04-01), Lim et al.
patent: 6646335 (2003-11-01), Emoto
patent: 6746895 (2004-06-01), Bolken et al.
patent: 2002/0041911 (2002-04-01), Mine
patent: 2005/0263873 (2005-12-01), Shoji

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