Semiconductor integrated circuit, method of designing the same a

Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator

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331 25, 331 1A, 331 14, 326 93, 327 12, 327156, 327293, 364490, H03L 700

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054205441

ABSTRACT:
A skew due to distribution of a clock inside a gate array is reduced. Phase comparators (14A), (14B) and (14C) are prepared in the peripheral portion of an internal circuit 71. The phase comparator (14C) is selected which is located nearest an element (77C) which receives an internal clock signal (65C) which is to be synchronized in terms of phase with an external clock signal (73). The selected phase comparator (14C) is connected to a charge pump circuit (16). Without forming a plurality of PLL circuits except for the phase comparators, the phase of any desired internal clock signal is synchronized with the phase of the external clock signal.

REFERENCES:
patent: 5075575 (1991-12-01), Shizukuishi et al.
patent: 5122679 (1992-06-01), Ishii et al.
patent: 5124569 (1992-06-01), Phillips
patent: 5150068 (1992-09-01), Kawashima et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5270592 (1993-12-01), Takahashi et al.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, Deog-Kyoon Jeong, et al., pp. 255-261, "Design of PLL-Based Clock Generation Circuits".

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