Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-06-05
2002-04-16
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S203000, C365S223000
Reexamination Certificate
active
06373783
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which includes memory cells. More particularly, it relates to a semiconductor integrated circuit capable of enhancing a bus occupation rate of data irrespective of the frequency of a clock signal. It also relates to a method of controlling the semiconductor integrated circuit for enhancing a bus occupation rate of data irrespective of the frequency of a clock signal.
The present invention also relates to a variable delay circuit capable of setting a delay time at a predetermined value.
2. Description of the Related Art
The operating speeds of semiconductor integrated circuits have steadily been heightened owing to the progress of semiconductor manufacturing technology. In particular, the operating frequency of a logic LSI such as microcomputer has yearly been improving and the difference thereof from the operating frequency of a memory LSI such as DRAM has been increasing.
In order to reduce such differences, there have been developed high-speed DRAMs such as EDO DRAM (Extended Data Output DRAM), SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate Synchronous DRAM), and Direct RDRAM (Rambus DRAM).
The high-speed DRAMs of this type are possible to read and write data from and into memory cells at high speed by successively accessing the memory cells connected to an identical word line. Concretely, there has been developed a DRAM whose maximum operating frequency exceeds 100 MHz. The high-speed DRAMs are often employed for the main storages of personal computers and workstations.
Meanwhile, the high-speed DRAMs of this type are used for not only personal computers and workstations but also the components of application products of microcomputers. In this case, the operating frequencies of the high-speed DRAMs are determined in accordance with the specifications of each product. Therefore, the operating frequency of the high-speed DRAM for such uses is set at, for example, 50 MHz or 75 MHz even in the case of setting the maximum operating frequency at 133 MHz.
When the high-speed DRAM is operated at the frequency lower than the maximum operating frequency, there arise some problems to be explained below.
FIG.
1
(
a
) shows a read timing when the cycle “tCK” of a clock signal CLK is 20 ns (50 MHz).
By way of example, an SDRAM performs a read operation by receiving a read command RD which activates a circuit relevant to column addresses after the reception of an activation command ACTV which activates a circuit relevant to row addresses. In the following description, commands shall be expressed as “ACTV command”, “RD command”, or the like.
In this SDRAM, the minimum time of a “tRCD” (/RAS to /CAS Delay time) is set at 18 ns. The tRCD is a time from the reception of the ACTV command to that of a command corresponding to a column address such as the RD command.
In addition, the minimum time of a “tCAC” (/CAS Access time from Clock) is set at 14 ns. The tCAC is a time from the reception of the command corresponding to the command address to the outputting of read data.
The tRCD, the tCAC, and a “tAC” indicated in FIG.
1
(
b
) are specifications necessary for properly operating the SDRAM and each value of them does not depend upon the operating frequency of the SDRAM in the identical products. In the following description, the clock signal CLK shall be called “CLK signal”.
In the case of operating the SDRAM at 50 MHz, the minimum time of the tRCD (18 ns) is less than the cycle of the CLK signal (20 ns). Therefore, the SDRAM can receive the RD command at the rising edge of the CLK signal (at 20 ns) as is next to that of the CLK signal corresponding to the reception of the ACTV command. The tRCD becomes 20 ns actually. In addition, the minimum time of the tCAC (14 ns) is less than the cycle of the CLK signal (20 ns). Therefore, the SDRAM outputs the read data QA
0
the tCAC (14 ns) after the rising edge of the CLK signal as corresponds to the reception of the RD command. As a result, an access time tRAC (/RAS Access time from Clock) from the reception of the ACTV command to the outputting of the read data QA
0
becomes 34 ns (tCK+tCAC).
On the other hand, FIG.
1
(
b
) shows a read timing in the case where the cycle “tCK” of a CLK signal is 13 ns (about 75 MHz).
Here, the maximum time of the “tAC” (Access time from Clock) is set at 6 ns. The tAC is a time from the rising edge of the clock signal to the outputting of read data.
In the case of operating the SDRAM at 75 MHz, the minimum time of a “tRCD” (18 ns) is greater than the cycle of the CLK signal (13 ns). Therefore, the SDRAM receives an RD command at the second rising edge of the CLK signal (at 26 ns) after the reception of an ACTV command. The tRCD becomes 26 ns actually. In addition, the minimum time of a “tCAC” (14 ns) is greater than the cycle of the CLK signal (13 ns). Therefore, the SDRAM outputs the read data QA
0
the tAC (6 ns) after the rising edge of the CLK signal next to that of the CLK signal corresponding to the reception of the RD command. As a result, an access time tRAC becomes 45 ns (3·tCK+tAC).
In the above read operations, the CLK signal at the higher frequency has the longer access time tRAC. In other words, the CLK signal at the higher frequency has the lower bus occupation rate of data, which causes a problem. Here, the “bus occupation rate” is a rate at which valid data are transmitted onto a data bus during a predetermined period. Therefore, the low bus occupation rate leads to degrading the performance of the whole system.
FIG.
2
(
a
) shows a precharge operation which proceeds after an ACTV command in the case where the cycle “tCR” of a clock signal CLK is 20 ns (50 MHz). The precharge operation is an operation of charging a bit line to a predetermined voltage so as to inactivate a circuit relevant to row addresses.
In this SDRAM, the minimum time of a “tRAS” (/RAS active time) is set at 24 ns. The tRAS is a time from the reception of an ACTV command to that of a precharge command PRE.
In addition, the minimum time of a “tRP” (/RAS Precharge time) is set at 10 ns. The tRP is a time from the reception of the PRE command to that of the next ACTV command. The tRAS, the tRP, and a “tDPL” indicated at FIG.
2
(
b
) are specifications necessary for properly operating the SDRAM and each value of them does not depend upon the operating frequency of the SDRAM in the identical products.
When operating the SDRAM at 50 MHz, the minimum time of the tRAS (24 ns) becomes greater than the cycle of the CLK signal (20 ns). Therefore, the SDRAM receives the PRE command at the second rising edge of the CLK signal (at 40 ns) after the reception of the ACTV command. The actual tRAS would be 40 ns. In addition, the SDRAM performs the precharge operation during the period of the tRP (10 ns) after the reception of the PRE command. Therefore, a cycle time “tRC” (/RAS Cycle time) from the reception of the ACTV command to that of the next ACTV command becomes 60 ns (3·tCK).
On the other hand, FIG.
2
(
b
) shows a write operation accompanying a precharge operation in the case where the cycle “tCK” of a clock signal CLK is 20 ns (50 MHz).
Here, a WRA command (WRite with Auto-precharge) is a command for causing the SDRAM to automatically perform the precharge operation after the write operation. The minimum time of a “tRCD” is set at 18 ns the same as in the ordinary read command RD (
FIG. 1
) or write command WR (not shown). The minimum time of a “tDPL” (Data-in to Precharge Lead time) is set at 10 ns. The tDPL is a time from the reception of write data to that of a precharge command PRE.
In operating the SDRAM at 50 MHz, the minimum time of the tRCD (18 ns) is less than the cycle of the CLK signal (20 ns) as in FIG.
1
(
a
). Therefore, the SDRAM can receive the WRA command at the rising edge of the CLK signal (at 20 ns) next to that of the CLK signal corresponding to the reception of an ACTV command.
The SDRAM simultaneously accepts the write data (not shown) with the WRA command and writes the
Arent Fox Kintner & Plotkin & Kahn, PLLC
Ho Hoai V.
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