Semiconductor integrated circuit manufacturing process providing

Fishing – trapping – and vermin destroying

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156646, H01L 21314

Patent

active

048762164

ABSTRACT:
In a method of semiconductor integrated circuit manufacture, a manufacturing process improvement provides highly planar, oxide-filled trench isolation of circuit device areas. The process improvement includes formation of a device area covered by a relatively thin insulating layer of oxide by a trenching process that forms a trench adjacent the device area. The thin insulating layer of oxide is extended over the side surface transition between the device area and the trench and then an insulating layer of crystalline dielectric material relatively thicker than the thin insulating layer is applied, which builds the trench at least to the level of the device area. A first layer of photoresist is applied over the thick insulating layer. The portion of the first photoresist layer overlying the device area is photolithographically removed, and then a second layer of photoresist is applied over the first layer; the second layer is applied to a thickness resulting in a relatively planar surface of photoresist overlying the trench and device area. All of the layers overlying the device area are removed by a process which operates toward the substrate surface on which the device area is formed. The removal process removes the first and second photoresist layers, the oxide of the relatively thin layer, and the crystalline dielectric material at substantially the same rate until the device area is expoded. When the device area is exposed, the removal process is terminated. The result provides a device area isolated by an oxide-filled trench, with the surface transition from the device area to the trench oxide being relatively planar.

REFERENCES:
patent: 4407851 (1983-10-01), Kurosawa et al.
patent: 4455740 (1984-06-01), Iwai
patent: 4543706 (1985-10-01), Bencuya et al.
patent: 4740480 (1988-04-01), Ooka

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