Semiconductor integrated circuit interconnection structures

Details Semiconductor integrated circuit interconnection structures Semiconductor integrated circuit interconnection structures

1992-04-24

1998-01-27

Whitehead, Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257750, 257764, 257901, 257904, H01L 2348, H01L 2352

Patent

active

057125090

ABSTRACT:
A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in the first electrically conducting interconnection layer proximate the through-hole extending to the first electrically insulating layer and filled with part of the second electrically insulating layer, constraining current flowing between the first and second electrically conducting interconnection layers to flow around the current barrier.

REFERENCES:
patent: 4884123 (1989-11-01), Dixit et al.
patent: 5101261 (1992-03-01), Maeda
Tomioka et al, "A New Reliability Problem Associated With Ar Ion Sputter Cleaning Of Interconnect Vias", IEEE/IRPS, pp. 53-58.
Nishida et al, "Multilevel Interconnection For Half-Micron ULSI'S", IEEE, VMIC Conference, Jun. 1989, pp. 19-25.
Abe et al, "High Peformance Multilevel Interconnection System With Stacked Interlayer Dieletrics By Plasma CVD And Bias Sputtering", IEEE, VMIC Conference, Jun. 1989, pp. 404-410.

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