Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-08-01
2002-11-26
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S203000
Reexamination Certificate
active
06487123
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a semiconductor integrated circuit, an ink cartridge having the semiconductor integrated circuit, and an inkjet recording device having the ink-cartridge attached, more particularly to a semiconductor integrated circuit having a non-volatile memory built in and using boosted voltage for data writing, an ink cartridge having the semiconductor integrated circuit, and an inkjet recording device having the ink cartridge attached.
2. Background Art
Conventionally, such a semiconductor integrated circuit performs a write operation by voltage boosted by an internal booster circuit when writing data on a built-in, non-volatile memory. At the end of writing, charge stored in a signal line charged at the time of writing is discharged before shifting to the next writing operation. In this case, the discharging is performed by a discharge circuit within a semiconductor integrated circuit.
FIG. 13
is a circuit diagram showing a discharge circuit in a conventional semiconductor integrated circuit. As shown in
FIG. 14
, the discharge circuit discharges charge stored in a parasitic capacitance Cx associated with each signal line of a memory cell array
5
. The parasitic capacitance Cx is charged in the following manner. An address counter
2
performs a count operation in response to an input of a write signal WR so that the address decoder
103
operates with the count value from counter
2
as input. The address decoder
103
includes a column decoder
4
and a row decoder
3
for respectively specifying a column and a row of memory cells from among the plurality of rows and columns of memory cells forming the memory cell array
5
. The memory cell array
5
includes a plurality of memory cells arranged in n rows by m columns.
Each output of the column decoder
4
, that is the decoded result, is input to the base terminal of a corresponding transistor Tr
1
, Tr
2
, . . . and Trm, which are switching elements. Then, a source terminal of each transistor is connected to a data line DW while drain terminal is connected to a signal line corresponding to each column of memory cells in the memory cell array
5
. Therefore, by turning any one of transistors Tr
1
, Tr
2
, . . . and Trm to the ON state with the output of the column decoder
4
, a signal line corresponding to each column is charged by voltage of the data line DW through the transistor. In other words, charge is stored in a parasitic capacitance of the signal line corresponding to the column specified by the column decoder
4
. For example, when the transistor Tr
1
is turned ON, charge is stored in a parasitic capacitance shown added to a signal line at a node A.
Here, an output of the input/output control circuit
8
is supplied to the data line DW. The input/output control circuit
8
includes an internal booster circuit
107
for boosting voltage of a power supply V
DD
in response to an input of the write signal WR, an inverter for generating an inverted signal of the write signal WR, a switching transistor
106
to whose gate terminal is supplied the output of the inverter
105
, which is the inverted signal of the write signal WR, and a buffer
108
supplying to data line DW a voltage corresponding to thy data value of input I/O. Buffer
108
receives as a power supply the output V
pp
of booster circuit
107
.
In the circuit
101
having such a construction, the write signal WR is at high level when writing to a memory cell while the transistor
106
is in the OFF condition. Here, the power supply V
DD
is supplied to the internal booster circuit
107
, resulting in a higher potential (15 volt, for example) for the boosted output V
PP
. The potential is supplied to the buffer
108
as a power supply. Thus, voltage corresponding to a value of the data input I/O is supplied from the buffer
108
to the data line DW. In this condition, turning any one of the transistors Tr
1
, Tr
2
, . . . to the ON condition results in a signal line of the corresponding column being charged by the voltage of the data line DW through the transistor. In the condition where the signal line is charged (the condition where charge is stored), data is written in each one of memory cells within the memory cell array
5
by the sequential changes in the outputs of the row decoder
3
.
ON the other hand, at the time of reading from a memory cells, and at other times, the write signal WR is at the low level and the transistor
106
is turned ON. At this time, the power supply V
DD
is not supplied to the internal booster circuit
107
, which turns the boosted output VPP to a lower non-boosted potential (5 volt, for example). The buffer
108
, which receives the lower, non-boosted potential V
pp
as its power supply, responds by bringing its output to the low level regardless of the value of the data input I/O. Therefore, the above-described stored charge are discharged through the data line DW to which the output of the buffer
108
is supplied. For example, the charge stored in the parasitic capacitance Cx shown added to node A is discharged toward ground through buffer
108
.
In short, in the conventional discharge circuit, by turning transistor
106
to the ON state at the end of a writing operation, the accumulated charge is discharged. However, in the semiconductor integrated circuit
101
having such a discharge circuit, there are problems as follows:
First of all, it takes time for removing charge completely. Thus, there is a problem that a certain amount of time is required before writing to the next memory cell.
Further, when the count value of the address counter changes at the same time as the end of a writing operation, residual charge in the parasitic capacitance resulting in higher voltage than expected, may lead to the error of wrong writing due to the parasitic capacitance not being completely discharged. The wrong writing will be described with reference to FIG.
14
.
In the figure, when writing on a X
1
column of memory cells, the transistor Tr
1
is turned ON by the column decoder
4
, first of all, and the parasitic capacitance Cx shown at node A is charged. In the charged condition, writing is performed by the row decoder
3
in order from row Y
1
, to row Y
2
. . . to row Yn. When each writing operation is completed, the parasitic capacitance Cx is discharged as described above. After the discharging following the writing operation to row Yn, the transistor Tr
2
corresponding to a next column of X
2
is turned ON by the column decoder
4
, and a next parasitic capacitance Cx is charged. In the charged condition, writing is performed by the row decoder
3
in order from row Y
1
, to row Y
2
. . . to row Yn. Charging and discharging is repeatedly on the remaining signal lines in similar manner. Through this operation, each 1 bit is addressed in order from column X
1
and row Y
1
to column Xm and row Yn, by which writing is performed on all memory cells of memory cell array
5
.
In the operation above, when transitioning from a writing operation on column X
1
and row Yn to a writing operation on column X
2
and row Y
1
, it may happen that row Y
1
is selected before the discharging of the signal line of column X
1
is fully complete. In this case, there is a problem the residual charge may cause wrong writing (i.e. writing to the wrong memory cell).
The present invention was made in order to overcome the problems of the above-describe conventional technology. A purpose of the present invention is to provide a semiconductor integrated circuit having a discharge circuit, that can surely discharge, an ink cartridge using it, and an inkjet recording device having the cartridge.
DISCLOSURE OF INVENTION
In a first aspect of the present invention, a memory addressing circuit sequentially cycles through all memory cells within a memory array when a memory circuit is placed in write mode of operation. Furthermore, a transition suppressing circuit, or delay circuit, inhibits the transitioning from a first addressed memory cell to the next addressed memory cell
Haro Rosalio
Mai Son
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