Semiconductor integrated circuit incorporating therein clock...

Details Semiconductor integrated circuit incorporating therein clock... Semiconductor integrated circuit incorporating therein clock...

1998-03-30

2001-04-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S115000

Reexamination Certificate

active

06211715

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit operated by a clock signal (hereinafter referring to as a clock). More particularly, this invention relates to a semiconductor integrated circuit into which a clock supply circuit is incorporated.
DESCRIPTION OF THE PRIOR ART
In a semiconductor integrated circuit such as single-micro chip computer which is operated by a clock, a clock corresponding to operation of a plurality of peripheral circuits provided within the circuit is required. For this reason, it is required that it causes clock inputted from external section to convert into clock with frequency which is required at respective peripheral circuits. As shown in
FIG. 1
, for example, Japanese Patent Application Laid-Open No. HEI 3-286213 discloses such a technology. A semiconductor integrated circuit
1
A disclosed therein comprises a first peripheral circuit
5
A, a second peripheral circuit
5
B, a third peripheral circuit
5
C, and a fourth peripheral circuit
5
D, a clock supply terminal
2
to which an external clock is supplied, and a clock supply circuit
3
X for supplying the supplied clock to respective peripheral circuits
5
A,
5
B,
5
C, and
5
D. Respective peripheral circuits
5
A to
5
D are connected to the clock supply circuit
3
X by wiring
9
.
FIG. 2
is a block diagram of the clock supply circuit
3
X. The clock supply circuit
3
X comprises a plurality of 1/2 frequency-dividing circuits
33
and clock drivers
34
. Respective clock drivers
34
possess current driving capability in answer to load capacity of respective clocks.
In the semiconductor integrated circuit
1
A, the clock supplied from the clock supply terminal
2
is divided into frequency-divided clock with frequency-divided ratio of 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 by selectively taking the output out from respective 1/2 frequency division circuits
33
with cascade connection in the clock supply circuit
3
X. The frequency-divided clock is supplied as respective required clocks at the above-described respective peripheral circuits
5
A to
5
D through the above-described wiring from the clock supply circuit
3
X.
FIG. 3
is a block diagram showing a semiconductor integrated circuit
1
B which is provided with a clock supply circuit which is different from the clock supply circuit
3
X of FIG.
1
. The semiconductor integrated circuit
1
B comprises a plurality of peripheral blocks
4
A,
4
B,
4
C, and
4
D. A peripheral block
4
A comprises a peripheral circuit
5
A, and a clock supply circuit
6
A. A peripheral block
4
B comprises a peripheral circuit
5
B and a clock supply circuit
6
B. A peripheral block
4
C comprises a peripheral circuit
5
C and a clock supply circuit
6
C. A peripheral block
4
D comprises a peripheral circuit
5
D and a clock supply circuit
6
D. The clock supply circuit of respective blocks is connected to a clock supply terminal
2
through wiring
10
and a clock driver
8
. In this semiconductor integrated circuit, the clock supplied from the clock supply terminal
2
is divided into frequency-divided clock with required frequency-divided ratio at the respective peripheral circuits
5
A,
5
B,
5
C, or
5
D in the respective clock supply circuits
6
A,
6
B,
6
C, or
6
D of the respective peripheral blocks
4
A,
4
B,
4
C, or
4
D to be supplied.
Now, in the above-described semiconductor integrated circuit as the conventional first technology shown in
FIG.1
, since it causes the clock with each different frequency-divided ratio to supply to the respective peripheral circuits
5
A to
5
D from one clock supply circuit
3
X through respective independent wirings, wiring length for transmitting clock is increased and, thus it is an obstacle to high integration of the semiconductor integrated circuit. Further, the wiring for transmitting clock with high frequency becomes long, and that fan out is numerous in the clock supply circuit, thus there is the problem that switching current becomes large.
In the semiconductor integrated circuit as the conventional second technology shown in
FIG. 3
, above-described problem of wiring length is loosened. However, it causes the clock with the highest frequency being in use at respective peripheral circuit
5
A to
5
D to supply to respective peripheral block
4
A to
4
D from the clock driver
8
to implement frequency dividing at the clock supply circuits
6
A to
6
D of respective peripheral blocks, thereby, the wiring of high frequency clock being in use at respective peripheral block becomes long, and fan out is numerous, there is also the problem that switching current becomes large.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention for achieving the above-mentioned object to provide a semiconductor integrated circuit which is provided with a clock supply circuit with low dissipation power, reducing switching current.
In accordance with one aspect of the present invention, for achieving the above-mentioned object, there is provided a semiconductor integrated circuit with a clock supply circuit having a plurality of peripheral circuits operated by frequency-divided clock, while dividing clock supplied from external section, the semiconductor integrated circuit comprises a first clock supply circuit which is capable of generating frequency-divided clock with the highest frequency among required frequency-divided clocks in the respective peripheral circuits, and a second clock supply circuit for generating frequency-divided clock which is required at the respective peripheral circuits from the frequency-divided clock of the first clock supply circuit. Preferably, there is provided a semiconductor integrated circuit with a clock supply circuit, wherein the first clock supply circuit is constituted as one clock supply circuit common to whole the plurality of peripheral circuits, and the second clock supply circuits are provided with corresponding to the respective peripheral circuits, thus generating frequency-divided clock required for respective corresponding peripheral circuits.
In accordance with another aspect of the present invention there is provided a semiconductor integrated circuit with a clock supply circuit, wherein the frequency-divided clock from the first clock supply circuit is supplied parallel to the respective second clock supply circuits, and the frequency-divided clock is supplied to respective corresponding peripheral circuits from the respective second clock supply circuits. Preferably, there is provided a semiconductor integrated circuit with a clock supply circuit wherein said respective second clock supply circuits are connected in cascade connection state, the frequency-divided clock from the first clock supply circuit is supplied to a first stage of the second clock supply circuit corresponding to the first peripheral circuit, then the frequency-divided clock from the second clock supply circuit is supplied to a second stage of the second clock supply circuit corresponding to the second peripheral circuit, hereinafter generally, the frequency-divided clock from a (n)-th stage of the second clock supply circuit is supplied in order to a (n+1)-th stage of the second clock supply circuit. Preferably, there is provided a semiconductor integrated circuit with a clock supply circuit, wherein a plurality of peripheral circuits divided into blocks in every smaller number than number of said plurality of peripheral circuits, a second clock supply circuit is provided corresponding to the respective blocks, the second clock supply circuit supplies the frequency-divided clock to respective peripheral circuits in the blocks.
The above and further objects and novel features of the invention will be more fully understood from the following detailed description when the same is read in connection with the accompanying drawings. It should be expressly understood, however, that the drawings are for purpose of illustration only and are not intended as a definition of the limits of the invention.


REFE

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit incorporating therein clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit incorporating therein clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit incorporating therein clock... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2494492