Semiconductor integrated circuit including conditional...

Details Semiconductor integrated circuit including conditional... Semiconductor integrated circuit including conditional...

2002-08-29

2003-10-07

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C327S212000

Reexamination Certificate

active

06630853

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-214326 filed on Jul. 23, 2002; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, particularly, a flip-flop circuit.
FIGS. 1A and 1B
show a known flip-flop circuit. In detail, FIG.
1
A and
FIG. 1B
show a signal-transfer circuit and a clock-supply circuit, respectively, of the known flip-flop circuit.
The signal-transfer circuit has a first clocked inverter INV
21
, the input node thereof being connected to an input D; a first inverter INV
22
connected in series to the output node of the first clocked inverter INV
21
; a second clocked inverter INV
23
interconnected with the first inverter INV
22
; a transmission gate TG
21
connected in series to the output node of the first inverter INV
22
; a second inverter INV
24
connected in series to the output node of the transmission gate TG
21
; a third clocked inverter INV
25
interconnected with the second inverter INV
24
; and a third inverter INV
26
connected in series to the output node of the second inverter INV
24
, the output of the third inverter INV
26
being connected to an output Q.
The clock-supply circuit has a fourth inverter INV
27
, the input node thereof being connected to a supply node for a clock signal CLK and a fifth inverter INV
28
connected in series to the output node of the fourth inverter INV
27
. An internal clock signal CKI is generated at the output node of the fifth inverter INV
28
and an inverted internal clock signal CKIB is generated at the output node of the fourth inverter INV
27
.
The internal clock signal CKI is supplied to N-channel MOS transistors of the second clocked inverter INV
23
and the transmission gate TG
21
and also P-channel MOS transistors of the first and the third clocked inverters INV
21
and INV
25
. The inverted internal clock signal CKIB is supplied to N-channel MOS transistors of the first and the third clocked inverters INV
21
and INV
25
and also P-channel MOS transistors of the second clocked inverter INV
23
and the transmission gate TG
21
.
Shown in
FIGS. 1A and 1B
are the internal clock and inverted clock signals supplied only to the N-channel MOS transistors for brevity.
A low-level clock signal CLK causes generation of a low-level internal clock signal CKI and a high-level inverted internal clock signal CKIB. On the contrary, a high-level clock signal CLK causes generation of a high-level internal clock signal CKI and a low-level inverted internal clock signal CKIB.
An input signal supplied via the input D is supplied to the first inverter INV
22
via the first clocked inverter INV
21
when the clock signal CLK is at a low level, or the inverted clock signal CKBI at a high level. The input signal supplied to the first inverter INV
22
is inhibited from being output therefrom because the transmission gate TG
21
and the second clocked inverter INV
23
have been turned of f by the low-level internal clock signal CKI.
On switching from the low to high level for the clock signal CLK, the first clocked inverter INV
21
is turned off whereas the transmission gate TG
21
and the second clocked inverter INV
23
is turned on. Therefore, on switching of the clock signal CLK, the input signal supplied via the input D is held by the first inverter INV
22
and the second clocked inverter INV
23
and further output from the output Q through the transmission gate TG
21
and the second and the third inverters INV
24
and INV
26
.
Next, on switching from the high to low level for the clock signal CLK, the transmission gate TG
21
is turned off whereas the third clocked inverter INV
25
is turned on. Therefore, on switching of the clock signal CLK, the input signal passed through the transmission gate TG
21
is held by the second inverter INV
24
and the third clocked inverter INV
25
and further output from the output Q through the third inverter INV
26
. This signal-transfer state continues until the transmission gate TG
21
is turned on again to receive another level of signal.
Any skilled in the art knows that flip-flop circuits consume much power in a large-scale integrated circuit (LSI).
The known flip-flop circuit shown in
FIGS. 1A and 1B
is charged and discharged at several nodes in accordance with operations based on the clock signal CLK, thus consuming power. Twelve transistors are charged and discharged among
24
transistors in total, for example, for the flip-flop circuit shown in
FIGS. 1A and 1B
, thus consuming power even if the input-signal level via the input D does not vary, which is about 40% of power consumed when the signal level varies.
The inventors Hamada et al. disclose a low-power-consuming flip-flop circuit in Japanese Unexamined Patent Publication No. 10-240713 corresponding to U.S. Pat. No. 6,204,707.
FIG. 2
shows a circuit block diagram of the disclosed flip-flop circuit.
The low-power-consuming flip-flop circuit has a first inverter INV
4
1
, the input node thereof being connected to an input D; a transmission gate TG
31
connected in series to the output node of the first inverter INV
41
; a second inverter INV
42
connected in series to the output node of the transmission gate TG
31
; a first clocked inverter INV
43
interconnected with the second inverter INV
42
; and a third inverter INV
44
connected in series to the output node of the transmission gate TG
31
, the output of the third inverter INV
44
being connected to an output Q.
The first and the second inverters INV
41
and INV
42
and the first clocked inverter INV
43
and also the transmission gate TG
31
constitute a latch as a signal-transfer circuit. An output Q is generated at the output node of the third inverter INV
44
for steady signal supply, although it can be generated at the output node of the second inverter INV
42
.
The low-power-consuming flip-flop circuit also has a pair of a first N-channel MOS transistor NM
21
and a first P-channel MOS transistor PM
21
connected in parallel, the drain of the MOS transistor NM
21
and also the source of the MOS transistor PM
21
being connected to the output node of the transmission gate TG
31
, the gate of the MOS transistor NM
21
being connected to the output node of the first inverter INV
41
, the gate of the MOS transistor PM
21
being connected to the input D; and another pair of a second N-channel MOS transistor NM
22
and a second P-channel MOS transistor PM
22
connected in parallel, the drain of the MOS transistor NM
22
and also the source of the MOS transistor PM
22
being connected to the output node of the second inverter INV
42
, the gate of the MOS transistor NM
22
being connected to the input D, the gate of the MOS transistor PM
22
being connected to the output node of the first inverter INV
41
.
The pair of the first N-channel MOS transistor NM
21
and the first P-channel MOS transistor PM
21
and the other pair of the second N-channel MOS transistor NM
22
and the second P-channel MOS transistor PM
22
constitute an EX-NOR logic circuit EX-NOR
3
for an exclusive-NOR operation to the D- and Q-inputs.
Moreover, the low-power-consuming flip-flop circuit has a 2-input AND logic circuit AND
21
, a clock signal CK being supplied to one of the inputs thereof; a 2-input NOR logic circuit NOR
21
, connected to one of the inputs thereof being the source of the first N-channel MOS transistor NM
21
, the drain of the first P-channel MOS transistor PM
21
, the source of the second N-channel MOS transistor NM
22
and the drain of the second P-channel MOS transistor PM
22
, connected to the other input of the 2-input NOR logic circuit NOR
21
being the output node of the AND logic circuit AND
21
; a 2-input NAND logic circuit NAND
21
, the clock signal CLK being supplied to one of the inputs thereof, connected to the other input thereof being the output node of the NOR logic circuit NOR
21
; a fourth inverter INV
45
, connected to the input thereof be

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