Semiconductor integrated circuit including command decoder...

Details Semiconductor integrated circuit including command decoder... Semiconductor integrated circuit including command decoder...

2000-03-30

2003-10-07

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06630850

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit which operates so as to accept input signals in synchronization with a clock signal.
2. Description of the Related Art
In general, semiconductor integrated circuits are broadly classified into logic LSIs, such as a microcomputer, and memory LSIs, such as a DRAM. The microcomputer has been widely known as a semiconductor integrated circuit which operates in synchronization with a clock. On the other hand, in the memory LSIs, an SDRAM (Synchronous DRAM) or the like operating in synchronization with a clock has been developed.
In the SDRAM, an interfacing circuit is operated at high speed in synchronization with a clock signal supplied from the exterior of the SDRAM, so that writing or reading data at high speed is made possible while timing margins are kept.
FIG. 1
shows the block diagram of an input interfacing circuit
1
in the semiconductor integrated circuit of this kind. The input interfacing circuit
1
includes a clock buffer
2
, a plurality of input buffers
3
a
,
3
b
,
3
c
, and a plurality of input signal accepting circuits
4
a
,
4
b
,
4
c
. Each of the input signal accepting circuits
4
a
,
4
b
,
4
c
includes a latch
5
. The clock buffer
2
is supplied with a clock signal CLK from the exterior of a chip. This clock buffer
2
decides the signal level of the clock signal CLK, converts the clock signal CLK into an internal clock signal CLKIN of high level or low level, and outputs the internal clock signal CLKIN to the respective input signal accepting circuits
4
a
,
4
b
,
4
c
. The input buffers
3
a
,
3
b
,
3
c
are respectively supplied with input signals S
1
, S
2
, S
3
from the exterior of the chip. These input buffers
3
a
,
3
b
,
3
c
decide the signal levels of the input signals S
1
, S
2
, S
3
, convert the input signals S
1
, S
2
, S
3
into internal signals SIN
1
, SIN
2
, SIN
3
of high level or low level, and output the internal signals SIN
1
, SIN
2
, SIN
3
to the input signal accepting circuits
4
a
,
4
b
,
4
c
, respectively. The latches
5
accept the internal signals SIN
1
, SIN
2
, SIN
3
in synchronization with the edge of the internal clock signal CLKIN, and output accepted signals SIN
1
A, SIN
2
A, SIN
3
A to a controlling circuit
6
, or the like within the chip, respectively. In the figure, lines indicated by arrows denote wiring patterns, and the directions of the arrows denote the directions in which the signals are transmitted.
In the input interfacing circuit
1
described above, ordinarily the input buffers
3
a
,
3
b
,
3
c
are arranged near pads for receiving the signals from the exterior of the chip and are dispersed on the chip. In contrast, the input signal accepting circuits
4
a
,
4
b
,
4
c
are arranged at the predetermined position on the chip. Therefore, the wiring patterns which are respectively laid to transmit the internal signals SIN
1
, SIN
2
, SIN
3
between the input buffers
3
a
,
3
b
,
3
c
and the input signal accepting circuits
4
a
,
4
b
,
4
c
can not have the same lengths. By way of example, the wiring pattern for transmitting the internal signal SIN
1
is the shortest, and the wiring pattern for transmitting the internal signal SIN
3
is the longest. Since the propagation delay time of each signal is proportional to the length of the wiring pattern, the internal signals SIN
1
, SIN
2
, SIN
3
are respectively supplied to the input signal accepting circuits
4
a
,
4
b
,
4
c
at timings different from one another.
As a result, the timings of the respective latches
5
for accepting the internal signals SIN
1
, SIN
2
, SIN
3
shift as shown in FIG.
2
. In the example of
FIG. 2
, the signal in which a timing margin for a set-up time tS is the smallest is the internal signal SIN
3
, and the signal in which a timing margin for a hold time tH is the smallest is the internal signal SIN
1
. Here, the “set-up time tS” is the specification of the minimum time in which the input signal needs to be settled before the rise of the clock signal CLK, and the “hold time tH” is the specification of the minimum time in which the input signal needs to be held after the rise of the clock signal CLK. Besides, in general, the ratings of external input terminals for the set-up time tS and the hold time tH are specified by the worst value of all input signals. For this reason, when the accepting timings of the internal signals SIN
1
, SIN
2
, SIN
3
fluctuates, the timing margins of the external input terminals for the set-up time tS and the hold time tH become short.
The specifications of the set-up time tS and the hold time tH need to be made more strict as the frequency of the clock signal CLK becomes higher. In the SDRAM of high speed operation, therefore, the input signal accepting circuits
4
a
,
4
b
,
4
c
are respectively furnished with delay circuits
7
a
,
7
b
,
7
c
on the input sides of the latches
5
as shown in
FIG. 3
, thereby to lower the fluctuation of the timings of the internal signals SIN
1
, SIN
2
, SIN
3
. In the figure, the sizes of the delay circuits
7
a
,
7
b
,
7
c
express the lengths of delay times. The delay circuits
7
a
,
7
b
,
7
c
are respectively adjusted in accordance with the delays of the internal signals SIN
1
, SIN
2
, SIN
3
attributed to the unequal lengths of the wiring patterns, and the timings at which the internal signals SIN
1
, SIN
2
, SIN
3
are respectively transmitted to the latches
5
are set same. In consequence, the set-up times tS and hold times tH of all the internal signals SIN
1
, SIN
2
, SIN
3
are equalized.
Meanwhile, in an SDRAM or the like, the combinations of the signal levels of a plurality of input signals received in synchronization with a clock signal CLK are decided as a plurality of controlling commands, by which an internal circuit is controlled.
As shown in
FIG. 4
, the input interfacing unit
1
of the SDRAM of this type is formed with a decoder
8
which receives accepted signals SIN
1
A, SIN
2
A, SIN
3
A output from respective latches
5
, and which outputs a command signal CMD.
With the circuit shown in
FIG. 4
, the output of the command signal CMD delayed because the internal signals SIN
1
A, SIN
2
A, SIN
3
A accepted by the corresponding latches
5
are decoded by the decoder
8
. As a result, the operation of a controlling circuit
6
delays, and an access time, or the like cannot be enhanced. In order to quicken the output of the command signal CMD, internal signals SIN
1
, SIN
2
, SIN
3
before being accepted by the latches
5
should be decoded.
Each of
FIGS. 5 and 6
shows the construction of the principal parts of an input interfacing unit
1
which serves to decode the internal signals SIN
1
, SIN
2
, SIN
3
before being accepted by the latches
5
, and which has been thought out by the inventors of the present invention.
The input interfacing unit
1
shown in
FIG. 5
is formed with a command accepting unit
9
which includes a decoder
10
, a delay circuit
7
d
and a latch [circuit]
5
. The decoder
10
receives the internal signals SIN
1
, SIN
2
, SIN
3
, and outputs a command signal CMD to the delay circuit
7
d
. The delay circuit
7
d
outputs the delayed command signal to the latch
5
. The latch
5
accepts the delayed command signal CMD in synchronization with an internal clock signal CLKIN, and outputs the accepted signal to the controlling circuit
6
as a command signal CMD
1
. Here, the delay circuit
7
d
is a circuit for adjusting the timings of the command signal CMD and the internal clock signal CLKIN which are supplied to the latch
5
.
The input interfacing unit
1
shown in
FIG. 6
is formed with a command accepting unit
11
which includes delay circuits
7
e
,
7
f
,
7
g
, a decoder
10
and a latch
5
. The decoder
10
receives the internal signals SIN
1
, SIN
2
, SIN
3
through the delay circuits
7
e
,
7
f
,
7
g
, respectively, and outputs a command signal CMD to the latch
5
. The latch

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