Semiconductor integrated circuit including bank selection...

Details Semiconductor integrated circuit including bank selection... Semiconductor integrated circuit including bank selection...

2008-01-23

2010-11-16

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

Reexamination Certificate

active

07835218

ABSTRACT:
A semiconductor integrated circuit according to one embodiment can include an up bank block that includes a first group of banks, a down bank block that includes a second group of banks, and a bank selection control block that provides up and down bank even-numbered global line control signals, up and down bank odd-numbered global line control signals, and up and down bank SDRAM write global line control signals in response to first and second group read control signals and a bank information signal in the up bank block and the down bank block. In this case, the bank selection control block may respond to a DDR signal and an SDR signal that are provided from an MRS (Mode Register Set).

REFERENCES:
patent: 6163491 (2000-12-01), Iwamoto et al.
patent: 6353574 (2002-03-01), Shim
patent: 6449198 (2002-09-01), Hamade et al.
patent: 6850444 (2005-02-01), Cho
patent: 09265775 (1997-10-01), None
patent: 2005-310345 (2005-11-01), None
patent: 2006-114192 (2006-04-01), None
patent: 1020030097025 (2003-12-01), None
patent: 1020070036492 (2007-04-01), None

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