Semiconductor integrated circuit having shield wire

Details Semiconductor integrated circuit having shield wire Semiconductor integrated circuit having shield wire

2000-02-28

2001-09-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Hardware for storage elements

Shields

C365S102000, C365S149000

Reexamination Certificate

active

06285573

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a shield wire.
2. Description of the Related Art
Throughout the development of high-speed computer systems, research into the enhancement of data processing speed of semiconductor integrated circuits has been continuous and vigorous. With ever-increasing data processing speed, designers are faced with the challenges of containing the increased interference between signal conductors, and of controlling increased noise generated during circuit operation. Thus, in order to maintain operating margins during high-speed operation, it is increasingly important to properly shield the generated interference and noise from primary signal conductors in order to avoid improper signal transitions.
FIG. 1
illustrates a first conventional technique for signal wire shielding in a semiconductor integrated circuit. In this example, neighboring signal conductors or wires
14
and
16
to be shielded are isolated from each other by a shield wire
12
electrically coupled to an external voltage source
10
. The external voltage source in turn applies a positive or negative source voltage or a ground voltage to the shield wire. The stable voltage serves as a barrier to noise and interference.
FIG. 2
illustrates a second conventional technique for signal wire shielding in a semiconductor integrated circuit. In this example, the signal wire
24
is electrically coupled to a first terminal of a decoupling capacitor
22
, and a second terminal of the decoupling capacitor
22
is electrically coupled to an external voltage source
20
. In this configuration, any noise components induced on the signal wire
24
by noise and interference generating sources are applied to, and absorbed by, the external voltage source
20
or the ground port, and therefore are prevented from adversely affecting nearby signal wires.
During operation, the voltage applied by the external voltage source can vary due to corresponding variances in operating current. As a result, in the conventional shielding configurations of
FIGS. 1 and 2
, instead of noise suppression, noise can be actively introduced on the signal wires
14
,
16
via shield wire
12
(
FIG. 1
) or on signal wire
24
via decoupling capacitor
22
(FIG.
2
). This, in turn, can cause the device to exhibit a reduced operating margin or worse, cause the device to malfunction.
SUMMARY OF THE INVENTION
In order to address the limitations of conventional techniques, it is an object of the present invention to provide a semiconductor integrated circuit having an enhanced shield wire configuration suitable for improving the operating characteristics.
Accordingly, to achieve the above object, there is provided a semiconductor integrated circuit including a plurality of signal wires and including a capacitor-based memory cell array. Capacitors in the array are coupled to a common voltage source node. At least one shield wire is positioned adjacent at least one signal wire. The at least one shield wire is electrically coupled to the common voltage source node.
In a preferred embodiment, a common electrical potential is applied to the common voltage source node of the memory cell capacitors, the electrical potential being different than that applied by an external voltage source. The at least one shield wire is preferably formed of a conductive material.
The at least one shield wire may be positioned between, or on opposite sides of, signal wires to be shielded. In the case where the circuit comprises a multiple-level circuit, the shield wires may be positioned between upper and lower levels to be shielded.
In accordance with another aspect of the present invention, a semiconductor circuit includes a capacitor-based memory cell array and a plurality of signal wires. Capacitors in the memory cell array are electrically coupled to a common voltage source node. The circuit comprises at least one shield capacitor, a first terminal of the shield capacitor being electrically coupled to the signal wire, and a second terminal of the shield capacitor being electrically coupled to the common voltage source node.
The shield capacitor preferably comprises a metal oxide silicon (MOS) capacitor.
In the semiconductor integrated circuit according to the present invention, the operating characteristics thereof can be improved by effectively shielding signal wires, without being adversely affected by variances in the voltage of external voltage sources and ground planes.


REFERENCES:
patent: 4514749 (1985-04-01), Shoji
patent: 4958222 (1990-09-01), Takakura et al.
patent: 5483110 (1996-01-01), Koide et al.
patent: 5616952 (1997-04-01), Nakano et al.

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