Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-09-06
2001-08-07
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000, C714S726000, C714S729000
Reexamination Certificate
active
06271700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit employing a scan path method for facilitating a test.
2. Description of the Related Art
A scale of a semiconductor integrated circuit has increased in company with progress toward higher integration and higher functionality thereof, with the result that the number of test patterns for use in detection of defects becomes immensely large. In order to achieve a higher defect detection rate with a smaller number of test patterns, the scan path method has been employed.
FIG. 12
shows a prior art semiconductor integrated circuit
10
employing this method.
A logic circuit in a circuit
10
includes a combinational circuit
11
and a sequential circuit, and the sequential circuit includes D flip-flops
12
to
15
. In
FIG. 12
, for simplicity of description, there is shown a case where the number of flip-flops is
4
. Internal output signals D
0
to D
3
of the combinational circuit
11
are provided to the respective data inputs D of the D flip-flops
12
to
15
, and outputs of the D flip-flops
12
to
15
are returned back to the combinational circuit
11
.
In order to make a scan path effective only in a scan mode, multiplexers
22
to
25
are provided in a correspondence with the respective D flip-flops
12
to
15
, and the internal output signals D
0
to D
3
of the combinational circuit
11
are provided to the respective data inputs D of the D flip-flops
12
to
15
through first inputs to the outputs of the respective multiplexers
22
to
25
. To the second inputs of the respective multiplexers
22
to
25
, a scan-in signal SIN and non-inverted outputs Q of the D flip-flops
12
to
14
, respectively, are provided. To the selection control inputs of the multiplexers
22
to
25
, a scan mode signal *SM is provided.
In a normal operating mode, the scan mode signal *SM is set high and the internal output signals D
0
to D
3
are selected by the multiplexers
22
and
25
, which makes a scan path ineffective.
In the scan mode, the scan mode signal *SM is set low and the scan-in signal SIN and output signals of the D flip-flops
12
to
14
are selected by the respective multiplexers
22
to
25
, which makes the scan path effective. The scan-in signal SIN is transferred through the scan path in synchronism with a clock CLK provided to the clock inputs CK of the D flip-flops
12
to
15
. After this transfer, to the combinational circuit
11
, patterns of input signals I
1
to In are provided with the scan mode signal *SM being set high, one pulse of the clock CLK is provided, and a pattern consisting of the output signals
01
to Om of the circuit
11
and the contents of the D flip-flops
12
to
15
are compared with an expected pattern. The contents of the D flip-flops
12
to
15
are taken out as a serial scan-out signal SOUT from the non-inverted output Q of the D flip-flop
15
through an output buffer circuit
30
by providing pulses of the clock CLK.
In the scan mode, when pulses of the clock CLK are provided and the contents of the D flip-flops
12
to
15
are serially read out, varying outputs of the D flip-flops
12
to
15
are also provided to the combinational circuit
11
. Thereby, not only the D flip-flops
12
to
15
and the output buffer circuit
30
, but also the combinational circuit
11
operate. For this reason, the D flip-flops
12
to
15
are required to be fabricated with transistors of large size so that no malfunction occurs because of shortage of drive capability of the scan path.
However, since a scan path becomes ineffective in the normal operating mode, if this requirement is met just to perform a temporary test, it causes power consumption to increases more than necessary not only in the scan mode but also in the normal operating mode.
Further, in simulation for verification of the test circuit (the scan path), the combinational circuit
11
operates when the contents of the D flip-flops
12
to
15
are serially taken out to the outside, which causes a time of simulation to be longer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide such a semiconductor integrated circuit that power consumption can be decreased, drive capability of a scan path required for a normal operation can be ensured, and further a time of simulation for verification of a test circuit can be decreased.
In one aspect of the present invention, there is provided a semiconductor integrated circuit comprising a logic circuit, the logic circuit including a combinational circuit and a sequential circuit, the sequential circuit including a plurality of flip-flops and having normal and scan paths made selectively effective by a scan mode signal, the normal and scan paths being constructed in such a way that, when the scan mode signal is inactive, the flip-flops receive output data of the combinational circuit through respective multiplexers on input sides or in input stages of the flip-flops, and when the scan mode signal is active, the flip-flops are cascaded through the multiplexers to form a shift register, the semiconductor integrated circuit further comprising: a gate circuit for preventing an output of at least one of the flip-flops from being transmitted to the combinational circuit when the scan mode signal is active.
With this aspect of the present invention, when the scan mode signal is active, the gate circuit is closed and its output remains unchanged even if a shift operation is performed on the scan path and therefore, power consumption in the combinational circuit can be decreased. Further, a drive capability of the scan path can be ensured even if the flip-flop whose output is connected to the gate circuit is configured with transistors having a smaller size than the prior art, thereby enabling decrease in power consumption not only in the scan mode, but also in the normal operating mode. Still further, in a simulation for verification of the test circuit (the scan path), a portion receiving the output of the gate circuit in the combinational circuit does not operate, therefore a time of simulation can be decreases.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.
REFERENCES:
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 5757203 (1998-05-01), Brown
Dinh Paul
Fujitsu Limited
Staas & Halsey , LLP
Wells Kenneth B.
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