Semiconductor integrated circuit having reduced crosstalk...

Details Semiconductor integrated circuit having reduced crosstalk... Semiconductor integrated circuit having reduced crosstalk...

2002-08-19

2003-12-16

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000

Reexamination Certificate

active

06664839

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which is readily capable of eliminating crosstalk noise which is generated on the reception side when sending clock signals in the same direction by using a plurality of wirings that are connecting the circuits.
2. Description of the Prior Art
The advancement of the processing speed of the computer or the like in recent years is remarkable, as exemplified by the operating speed of several hundreds MHz for the microprocessor of the personal computer, and a high rate data transfer in the band of several GHz is being obliged in the network market. Accompanying such a trend, the electrical signals that flow in the wirings (signal lines) that connect circuits within the IC become also high rate, making the effect of crosstalk between adjacent signals increasingly conspicuous.
Since the crosstalk gets the larger the smaller the distance between the wirings, it is a factor of obstruction standing in the way toward miniaturization and high density of the high speed circuit. In particular, when the width of data handled becomes large such as 32 bits or 64 bits, propagation of many signals in the same direction occurs more frequently, and the possibility of causing malfunctions of the system is increased due to superposition of noises of a plurality of noise sources.
FIG. 19
is a circuit diagram showing the internal configuration of a conventional semiconductor integrated circuit.
FIG. 19
shows a circuit in which a plurality of clock signals CK
1
to CK
8
having identical delay difference between the signals, output from a delay locked loop (referred to as DLL hereinafter) circuit
101
, are supplied to a data comparator (referred to as DCMP hereinafter) via an insert part
1402
.
The DLL circuit
101
generates n (n is an integer of 2 or more, and it is 8 in this example) clock signals Cki (i is an integer of 1 to n) each of them being delayed by a delay time of i×T (T is a constant time) from a reference signal RCLK. In the buffer insert part
1402
, there are provided buffers B
1
to B
8
corresponding to the clock signals CK
1
to CK
8
. The buffers B
1
to B
8
are provided to prevent the attenuation of respective clock signals CK
1
to Ck
8
by the parasitic capacitances and the parasitic resistances of the wirings that connect the DLL circuit
101
to the DCMP circuit
103
.
The clock signals CK
1
to CK
8
output from the DLL circuit
101
are input respectively to the input terminals of the buffers B
1
to B
8
via input wirings NI
1
to NI
8
. The clock signals CK
1
to CK
8
output from the output terminals of the buffers B
1
to B
8
are input respectively to the corresponding input terminals of the DCMP circuit
103
via output wirings NO
1
to NO
8
.
In
FIG. 19
, CI
1
, CI
2
, CI
3
, CI
4
, CI
5
, CI
6
and CI
7
represent the parasitic capacitances present between the input wirings NI
1
and NI
2
, between NI
2
and NI
3
, between NI
3
and NI
4
, between NI
4
and NI
5
, between NI
5
and NI
6
, between NI
6
and NI
7
and between NI
7
and NI
8
, respectively. Similarly, CO
1
, CO
2
, CO
3
, CO
4
, CO
5
, CO
6
and CO
7
represent the parasitic capacitances present between output wirings NO
1
and NO
2
, between NO
2
and NO
3
, between NO
3
and NO
4
, between NO
4
and NO
5
, between NO
5
and NO
6
, between NO
6
and NO
7
and between NO
7
and NO
8
, respectively.
FIG. 20
is a waveform diagram showing the clock signals CK
1
and CK
2
, and the signals on the input wirings NI
1
and NI
2
connected to the input terminals of the buffers B
1
and B
2
. The NI
1
in
FIG. 20
shows the clock signal flowing on the input wiring NI
1
, and the NI
2
in
FIG. 20
shows the clock signal CK
2
flowing on the input wiring NI
2
.
The rise edge tr of the clock signal CK
1
is propagated to the input terminal of the buffer B
1
through the input wiring NI
1
. Owing to the parasitic capacitance CI
1
and a wiring resistance, not shown, the tr edge of the clock signal CK
1
arrives at the input terminal of the buffer B
1
after a delay time of &tgr;1. Moreover, the rise edge tr of the clock signal CK
2
is propagated to the input terminal of the buffer B
2
through the input wiring NI
2
. Owing to the parasitic capacitances CI
1
and C
2
and wiring resistances, not shown, the tr edge of the clock signal CK
2
arrives at the input terminal of the buffer B
2
with a delay time of &tgr;2 after leaving the DLL circuit
101
.
At this time, due to the fact that the input wiring NI
1
of the buffer B
1
and the input wiring NI
2
of the buffer B
2
are disposed adjacent in parallel, crosstalk noise caused by the tr edge of the clock signal CK
1
mingles with the clock signal CK
2
on the input wiring NI
2
via the parasitic capacitance CI
1
.
As can be seen from
FIG. 20
, the edge tr of the clock signal CK
2
flowing on the input wiring NI
2
is located, as seen on the time base, in the vicinity of the edge tr of the clock signal CK
1
flowing on the input wiring NI
1
.
Accordingly, low level of the clock signal CK
2
flowing on the input wiring NI
2
fluctuates as shown in
FIG. 20
due to the effect of the crosstaslk, and a deviation corresponding to a minute time &Dgr;tr is generated in the tr edge of the clock signal CK
2
on the input wiring NI
2
. In this manner, the crosstalk noise affects the tr edge of the clock signal CK
2
flowing on the input wiring NI
2
.
Analogously, the crosstalk noise caused by the tr edge of the clock signal CK
2
mingles with the clock signal CK
1
flowing on the input wiring NI
1
via the parasitic capacitance CI
1
. The crosstalk noise affects the tr edge of the clock signal CK
1
flowing on the input wiring NI
1
, and generates a deviation of a minute time in the tr edge of the clock signal CK
1
.
Although the tr edge of rise alone has been mentioned in the above, similar situation occurs of course concerning the tf edge of the fall. For example, crosstalk noise caused by the tf edge of the clock signal CK
1
mingles with the clock signal CK
2
on the input wiring NI
2
via the parasitic capacitance CI
1
. The crosstalk noise affects the tf edge of the clock signal CK
2
flowing on the input wiring NI
2
, and generates a deviation corresponding to a minute time &Dgr;tf in the clock signal CK
2
.
As in the above, although no time difference exists between the tr edge and the tf edge of each of the adjacent clock signals CK
1
to CK
8
in the semiconductor integrated circuit in
FIG. 19
, deviations of minute time &Dgr;tr and &Dgr;tf are generated respectively in the tr edge and the tf edge of respective clock signals CK
1
to CK
8
, owing to the effect of crosstalk noise generated by the interference between respective adjacent clock signals CK
1
to CK
8
. This fact gives rise to a problem of increase in the skew (phase deviation) among the clock signals CK
1
to CK
8
, and jitter (phase fluctuation) in each of the clock signals CK
1
to CK
8
.
Generally, crosstalk noise attenuates in inverse proportion to the distance between the clock signals. Consequently, the solution to the problem will be obtained by simply taking the spacing between the signal lines large enough. However, taking the spacing between the signal lines large leads to an increase in the wiring area, and results in a large area of the IC which makes it fail to be a practical solution.
Next, by making correspondence to the circuit diagram in
FIG. 19
, a design method for determining the circuit layout and wiring of the semiconductor integrated circuit will be described in detail.
FIG. 21
is a diagram showing a series of flows as will be described in the following. It starts with determination step
1602
of the layout positions of the DLL circuit
101
and the DCMP circuit
103
, and after determination of the layout and wiring of the buffer insert part
1402
, confirms the skews between the clock signals CK
1
to CK
8
and the jitters of the clock signals CK
1
to CK
8
in the buffer in

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