Semiconductor integrated circuit having protection circuits

Details Semiconductor integrated circuit having protection circuits Semiconductor integrated circuit having protection circuits

1993-07-23

1996-07-09

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

257356, 361 91, 361111, H01L 2362, H02H 902

Patent

active

055350844

ABSTRACT:
This invention provides a semiconductor integrated circuit including protection circuits which are protective against static electricity corresponding to an area of internal cells, and are adaptable to excessive voltages generated under complicated conditions, such as ESD pulses, etc. The semiconductor integrated circuit comprises a plurality of input/output cells connected electrically in parallel to one bonding pad, and a plurality of protection circuits for decreasing excessive voltages arranged in parallel between the bonding pad and the I/O cells. The wiring patterns between the parallel-arranged protection circuits and the I/O cells are shorted together.

REFERENCES:
patent: 4942317 (1990-07-01), Tanaka et al.
patent: 4945395 (1990-07-01), Suehiro
patent: 5079612 (1992-07-01), Takamoto et al.
Robert J. Antinone, et al., "Electrical Overstress Protection for Electronic Devices", Noyes Publications, New Jersey, 1986, pp. 16-19.

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