Semiconductor integrated circuit having power supply pin

Details Semiconductor integrated circuit having power supply pin Semiconductor integrated circuit having power supply pin

2000-05-12

2002-09-17

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S909000, C257S905000, C257S666000, C257S691000, C257S697000

Reexamination Certificate

active

06452269

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically, it relates to a synchronous SRAM supplied with two types of power supply voltages.
2. Description of the Background Art
A synchronous SRAM (static random access memory) mainly comprises two power sources for power supplied to an internal circuit and power for an input/output circuit deciding an input/output level. This is because a voltage optimum for the synchronous SRAM to keep a high speed itself and a voltage optimum for a logic chip of a CPU (central processing unit) or a chip set directly connected with the synchronous SRAM are different from each other.
More specifically, power Vdd for the internal circuit of the synchronous SRAM is generally 3.3 V (or 2.5 V as the case may be), and power VddQ for the input/output circuit is 2.5 V or 1.8 V. The power VddQ is equalized with a power supply voltage supplied to a peripheral logic chip of the synchronous SRAM. When the power VddQ is set to 2.5 V or 1.8 V, the synchronous SRAM the input/output level of the synchronous SRAM reaches a CMOS (complementary metal-oxide semiconductor) level of 2.5 V or 1.8 V (a high level is 2.5 V or 1.8 V, and a low level is 0 V).
As typical examples of such a synchronous SRAM,
FIGS. 12 and 13
show a type
1
pipelined burst SRAM and
FIGS. 14 and 15
show a synchronous network SRAM respectively. The synchronous network SRAM is an advanced standard synchronous SRAM in the process of standardization in JEDEC (Joint Electron Device Engineering Council). In the following description, pins and signals corresponding to the pins are denoted by the same reference numerals.
FIG. 12
illustrates the pin arrangement of the type
1
pipelined burst SRAM. Referring to
FIG. 12
, fifteenth, forty-first, sixty-fifth and ninety-first pins are power supply pins Vdd for an internal circuit, seventeenth, fortieth, sixty-seventh and ninetieth pins are ground power supply pins Vss for the internal circuit, fourth, eleventh, twentieth, twenty-seventh, fifty fourth, sixty-first, seventieth and seventy-seventh pins are power supply pins VddQ for an output buffer, and fifth, tenth, twenty-first, twenty-sixth, fifty-fifth, sixtieth, seventy-first and seventy-sixth pins are ground power supply pins VssQ for the output buffer.
Fifty-second, fifty-third, fifty-sixth to fifty ninth, sixty-second and sixty-third pins are data input/output pins DQa, sixty-eighth, sixty-ninth, seventy-second to seventy-fifth, seventy-eighth and seventy-ninth pins are data input/output pins DQb, second, third, sixth to ninth, twelfth and thirteenth pins are data input/output pins DQc, and eighteenth, nineteenth, twenty-second to twenty-fifth, twenty-eighth and twenty-ninth pins are data input/output pins DQd. Fifty-first, eightieth, first and thirtieth pins are parity data input/output pins DQPa, DQPb, DQPc and DQPd.
Thirty-second to thirty-fifth, forty-fourth to fiftieth, eighty-first, eighty-second, ninety-ninth and hundredth pins are address input pins A, and thirty-seventh and thirty-sixth pins are address input pins A
0
and A
1
. An eighty-ninth pin is a clock input pin CLK. Ninety-second, ninety seventh and ninety-eighth pins are chip enable input pins CUE#, CE
2
and CE
1
#. Eighty-third, eighty-fourth and eighty-fifth pins are burst control pins ADV#, ADSP# and ADSC#.
Eighty-eighth, eighty-seventh, ninety-third, ninety-fourth, ninetyfifth and ninety-sixth pins are write control input pins GW#, BWE#, BWa#, BWb#, BWc# and BWd#. An eighty-sixth pin is an output enable pin OE#, a sixty-fourth pin is a snooze mode (power sleep mode) input pin ZZ, a fourteenth pin is a flow-through input pin FT#, and a thirty-first pin is a linear burst input pin LBO#. Sixteenth, thirty-eighth, thirty-ninth, fortysecond, forty-third and sixty-sixth pins are non-connected pins NC.
FIG. 12
shows exemplary pin arrangement, and the forty-third non-connected pin NC is replaced with an address input pin in the case of 9 Mbits, for example. Further, any or all of the flow-through input pin FT#, the linear burst input pin LBO# and the snooze mode input pin ZZ may not be supported.
As shown in
FIG. 13
, the type
1
pipelined burst SRAM comprises control registers
21
and
22
, a control logic circuit
23
, logic circuits
27
and
28
, a burst control logic circuit
24
, an address register
25
, a burst address counter
26
, a memory cell array
30
, a data input register
31
, a data output register
34
and an output buffer
35
.
The control register
21
captures burst control signals ADV# and ADSC# in synchronization with a clock signal CLK. The burst control logic circuit
24
captures a linear burst signal LBO# and the value of the control register
21
in synchronization with the clock signal CLK, and outputs an internal control signal for a burst operation.
The logic circuit
27
receives a burst control signal ADSP# and a chip enable signal CE
1
#. The logic circuit
28
receives chip enable signals CE
1
#, CE
2
and CE
3
#.
The control register
22
captures outputs of the logic circuits
27
and
28
and write control signals GW#, BWE# and BWa# to BWd# in synchronization with the clock signal CLK.
The control logic circuit
23
receives the value of the control register
22
, the output of the burst control logic circuit
24
, an output enable signal OE# and a snooze mode signal ZZ and outputs a corresponding internal control signal.
The address register
25
captures addresses A
0
to A
16
in response to the output of the burst control logic circuit
24
. The addresses A
0
and A
1
are output to the burst address counter
26
. The burst address counter
26
outputs addresses A′
0
and A′
1
in response to control by the burst control logic circuit
24
. A burst sequence (linear burst or interleaved) is selected with the linear burst signal LBO#.
The memory cell array
30
includes a plurality of memory cells arranged in rows and columns. A corresponding memory cell is selected on the basis of the output of the burst address counter
26
and the addresses A
1
to A
16
from the address register
25
.
Data buses DBO to DB
35
are provided in correspondence to the data input/output pins DQa (eight), DQb (eight), DQc (eight) and DQd (eight) and the parity data input/output pins DQPa to DQPd respectively.
The data input register
31
captures data from the data buses in response to control by the control logic circuit
23
. The data input register
31
captures data from the data input/output pins DQa with the write control signal BWa#, data from the data input/output pins DQb with the write control signal BWb#, data from the data input/output pins DQc with the write control signal BWc# and data from the data input/output pins DQd with the write control signal BWd#. The data captured in the data input register
31
are written in the selected memory cell.
The data output register
34
captures data read from the selected memory cell in response to control by the control logic circuit
23
. The output buffer
35
outputs the data captured in the output register
34
to the data buses in response to control by the control logic circuit
23
.
All input signals excluding the linear burst signal LBO#, the output enable signal OE# and the snooze mode signal ZZ are captured in synchronization with the clock signal CLK.
36-bit write operations are controlled with the write control signal GW#. The write operations are executed byte by byte with the write control signals BWa# to BWd# and BWE#. A burst operation is controlled with the burst control signal ADSC# or ADSP#. The burst control signal ADV# controls a burst address. A read operation is initialized with the burst control signal ADSP#.
The overall chip enters a power down mode with the snooze mode signal ZZ, for saving a standby current.
FIG. 14
illustrates pin arrangement of the

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