Semiconductor integrated circuit having plural input control...

Details Semiconductor integrated circuit having plural input control... Semiconductor integrated circuit having plural input control...

1999-10-15

2001-10-30

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S122000, C341S155000, C341S158000

Reexamination Certificate

active

06310572

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits that include series-parallel type analog-to-digital converters having analog signal processing circuits.
A series-parallel type analog-to-digital (A/D) converter includes an upper rank comparator, which performs A/D conversion of upper rank bits, and a lower rank comparator, which performs A/D conversion of lower rank bits. The upper rank comparator samples analog input signals and compares the sampled signals with an upper rank reference voltage signal. The lower rank comparator samples analog input signals and compares the sampled signals with a lower rank reference voltage signal, which is based on the comparison result of the upper rank comparator. The A/D converter combines the comparison results of the upper and lower rank comparators to generate a digital signal. Thus, the sampling level of the upper rank comparator and that of the lower rank comparator must be substantially the same. The upper and lower rank comparators must perform sampling at precisely the same timing to obtain sampling levels that are substantially the same. However, differences in the load conditions of sample and hold (S/H) control signals, differences in the lengths of wires, and other factors cause unsynchronized sampling. This results in the upper and lower rank comparators sampling different analog input signals and affects the linearity of signals when combining the output signals of the upper rank and lower rank comparators.
FIG. 1
is a schematic circuit diagram showing a prior art series-parallel type comparator
10
. The A/D converter
10
includes an upper rank comparator
11
and a lower rank comparator
12
. The upper rank comparator
11
includes voltage comparators CM
U1
-CM
Um
, the number m of which corresponds to the number of upper rank bits in the digital signal. The lower rank comparator
12
includes voltage comparators CM
L1
-CM
Ln
, the number n of which corresponds to the number of lower rank bits. The voltage comparators CM
U1
-CM
Um
, CM
L1
-CM
Ln
are chopper type voltage comparators. Each voltage comparator CM
U1
-CM
Um
, CM
L1
-CM
Ln
samples an analog input signal V
in
and compares the sampled level with reference voltages V
U1
-V
Um
, V
L1
-V
Ln
, respectively.
FIG. 3
is a schematic circuit diagram showing the voltage comparator CM
U1
. Since each voltage comparator CM
U1
-CM
Um
, CM
L1
-CM
Ln
has the same structure, only the voltage comparator CM
U1
will be described in detail.
The voltage comparator CM
U1
includes switches SW
1
-SW
3
, a capacitor C
1
, an inverter
13
, and a flip-flop (FF)
14
. The input terminals which receive the analog input signal V
in
and the reference voltage V
U1
are connected to a first input terminal (node N
1
) of the capacitor C
1
via the switches SW
1
, SW
2
, respectively. The switches SW
1
, SW
2
are opened and closed in accordance with control signals S
1
u, S
2
u, respectively. The control signals S
1
u, S
2
u are output from a control signal generator (not shown). The respective switches SW
1
, SW
2
are closed when the control signals S
1
u, S
2
u are high (H-level).
The capacitor C
1
has a second terminal (node N
2
), which is connected to the data input terminal of the FF
14
via the inverter
13
. The switch SW
3
is opened and closed in accordance with the control signal S
1
u. The switch SW
3
closes when the control signal S
1
u is high. The FF
14
latches the input signal in response to the control signal S
2
u and outputs a latch signal Out.
FIG. 4
is a timing chart showing the operation of the voltage comparator CM
U1
. If the control signal S
1
u is at the H-level, or is “high”, while the control signal S
2
u is at the L-level, the switches SW
1
, SW
3
are ON and the switch SW
2
is OFF. In this state, the inverter
13
is biased at a threshold voltage Vt and electric charge (C
0
×(V
in
−Vt)) is stored in the capacitor C
1
. C
0
represents the capacitance value of the capacitor C
1
and V
in
represents the voltage of the analog input signal. This operation is referred to as auto zero, during which the analog input signal V
in
is stored in the capacitor C
1
when the voltage comparator CM
U1
is biased at the threshold voltage.
When the control signal S
1
u shifts to the L-level and the control signal S
2
u shifts to the H-level, the switches SW
1
, SW
3
are opened and the switch SW
2
is closed. In this state, the node N
2
enters an electrically floating state. Thus, according to the charge conservation law, the charge stored in the capacitor C
1
does not change. The application of the upper rank reference voltage V
U1
, instead of the analog input signal V
in
to the node N
1
, or the capacitor C
1
, sets a potential V
2
at the node N
2
at Vt+V
U1
−V
in
since charge is conserved in the capacitor C
1
. In other words, the potential V
2
changes from the threshold voltage Vt by (V
U1
−V
in
). The voltage V
2
is reverse-amplified by the inverter
13
and a potential having a level which logic value can sufficiently be distinguished by the FF
14
is generated. The FF
14
is strobed when the potential at the node N
3
is stabilized (final point during comparison) to generate a logic signal Out.
Accordingly, the A/D converter
10
operates as shown in FIG.
2
. If the control signals S
1
u, S
1
v are at the H-level, while the control signals S
2
u, S
2
v are at the L-level, the voltage comparators CM
U1
-CM
Um
, CM
L1
-CM
Ln
of the upper and lower rank comparators
11
,
12
each performs the auto zero operation, while receiving the analog input signal V
in
. Afterward, when the control signals S
1
u, S
2
u shift to the L-level, each voltage comparator CM
U1
-CM
Um
, CM
L1
-CM
Ln
stores the voltage of the analog input signal V
in
just before the control signals S
1
u, S
2
u shift from the H-level to the L-level.
In response to an H-level control signal S
2
u, the upper rank comparator
11
compares the analog input signal V
in
with the upper rank reference voltages V
U1
-V
Um
and A/D converts the upper rank bits, while designating the lower rank reference voltages V
L1
-V
Ln
of the lower rank comparator
12
based on the comparison results.
After performing the auto zero operation simultaneously with the upper rank comparator
11
, the lower rank comparator
12
shifts all of the switches SW
1
-SW
3
to OFF (i.e., open) and stores the analog input signal V
in
while waiting until the upper rank comparator
11
determines the lower rank reference voltages V
L1
-V
Ln
(i.e., until the upper rank bits are determined). The lower rank comparator
12
then compares the analog input signal V
in
with the lower rank reference voltages V
L1
-V
Ln
and A/D converts the lower bits. The A/D converter
10
combines the upper rank bits from the upper rank comparator
11
with the lower rank bits from the lower rank comparator
12
and generates an A/D converted signal.
The upper and lower rank comparators
11
,
12
must simultaneously shift from a sampling state to a holding state in order to receive analog input signals having the same level during sampling. However, it is impossible to control every switch SW
1
of the voltage comparators CM
U1
-CM
Um
, CM
L1
-CM
Ln
at the same timing. With reference to
FIG. 2
, the sampling tolerance voltage between the upper and lower rank comparators
11
,
12
is denoted as Ve. If S represents the changing rate of the analog input signal V
in
and te[ns] represents the sample and hold timing tolerance between the upper rank comparator
11
and the lower rank comparator
12
, S×te represents the sampling tolerance voltage Ve. Accordingly, the timing tolerance te that is allowed decreases as the changing rate S increases. In other words, the sampling tolerance of the upper and lower rank comparators
11
,
12
is narrowed.
The arrangement of a sample and hold (S/H) circuit upstream of the A/D converter
10
shifts the changing rate S of the analog input signal to a va

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