Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
2000-02-24
2004-08-03
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C327S382000, C327S566000
Reexamination Certificate
active
06771112
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit that employs pads providing less input signal attenuation.
(b) Description of Related Art
Junction field-effect transistors (abbreviated as J-FETS) are generally used for special applications such as condenser microphones because they have a high input impedance, compared with bipolar elements, and a high electrostatic withstand voltage, compared MOS FET elements. Moreover, J-FETs are used for small signal amplification because of less noise over low-frequencies and good high-frequency characteristics. Recently, J-FETs built in a bipolar integrated circuit are being developed.
FIG. 6
shows an integrated circuit integrating a J-FET. A signal is applied to the gate of the J-FET
2
from an external circuit via a pad
1
formed on an integrated substrate. The external input signal varies the gate voltage of the J-FET
2
, thus varying the current amount flowing through the J-FET
2
. The load resistance RL converts the current into a voltage to output the converted voltage.
In the integrated circuit shown in
FIG. 6
, two parasitic capacitance components occur between the pad
1
and the substrate. Referring to the cross section of an integrated pad shown in
FIG. 7
, an island region
102
is defined between two isolation regions
101
. A metal
103
is formed over the island region
102
. In such an integrated configuration, a MOS capacitance (or parasitic capacitance)
3
is formed between the island region
102
and the metal
103
. A junction capacitance (or parasitic capacitance)
4
is formed between the island region
102
and the substrate. The juncture between the pad
1
and the gate of the J-FET
2
, as shown in
FIG. 3
, is grounded via the parasitic capacitances
3
and
4
. Where an element with a high output impedance, for example, a capacitor of a small capacitance, is connected to the pad
1
, both the parasitic capacitances
3
and
4
may appear as a very large capacitance, compared with the small capacitor. Particularly, when the area of the pad
1
is made large to use the circuit of
FIG. 3
for a special application, the parasitic capacitance becomes even larger so that the difference between the capacitance of the small capacitor and the parasitic capacitance becomes noticeable. As a result, since the pad
1
attenuates the input signal applied to the gate of the J-FET
2
, it is difficult to erroneously obtain the input signal.
SUMMARY OF THE INVENTION
This invention is made to overcome the above-mentioned problems. It is an object of the present invention to provide a semiconductor integrated circuit including pads each with a high input impedance and with a low capacitance.
The pad is connected to a buffer circuit that charges and discharges the parasitic capacitance. Thus, the charging amount of the parasitic capacitance varies according to an input signal so that attenuation of an input signal can be prevented.
The pad is connected to a source follower circuit that charges and discharges the parasitic capacitance. Thus, the charging amount of the parasitic capacitance varies according to an input signal so that attenuation of an input signal can be prevented.
REFERENCES:
patent: 4675561 (1987-06-01), Bowers
patent: 4700461 (1987-10-01), Choi et al.
patent: 4875019 (1989-10-01), Monson et al.
patent: 5469104 (1995-11-01), Smith et al.
patent: 5534815 (1996-07-01), Badyal
patent: 5550503 (1996-08-01), Garrity et al.
patent: 5847381 (1998-12-01), Isogai
patent: 6175278 (2001-01-01), Hasegawa
Weste et al., “Principles of CMOS VLSI Design: A Systems Perspective”, 1994, Addison-Wesley Publishing Company, 2ndedition, pp. 183-186.
Ishikawa Tsutomu
Kojima Hiroshi
Cantor & Colburn LLP
Nguyen Long
Sanyo Electric Co., Inc.
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