Semiconductor integrated circuit having oxide regions with diffe

Details Semiconductor integrated circuit having oxide regions with diffe Semiconductor integrated circuit having oxide regions with diffe

1988-06-30

1991-10-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437 47, 437 48, 437 52, 437 60, 437 69, 437235, 437919, 357 235, 357 236, H01L 2170

Patent

active

050616544

ABSTRACT:
A method of manufacturing a semiconductor memory device having a peripheral circuit portion, the operating voltage of which is relatively high and a memory array portion, the operating voltage of which is relatively low comprises the steps of forming an inversion preventing layer on the peripheral circuit portion, forming an oxide layer for isolation between devices adjacent thereto, forming on the memory array portion the inversion preventing layer, the impurity concentration of which is higher than that of the peripheral circuit portion and forming the oxide layer on the peripheral circuit portion at the same time that the oxide layer for isolation between devices is formed adjacent thereto.

REFERENCES:
patent: 3855008 (1974-12-01), Huber et al.
patent: 4208781 (1980-06-01), Rao et al.
patent: 4352236 (1982-10-01), McCullom
patent: 4384399 (1983-05-01), Kuo
patent: 4385432 (1983-05-01), Kuo et al.
patent: 4412375 (1983-11-01), Matthews
patent: 4536947 (1985-08-01), Bohr et al.
patent: 4561170 (1985-12-01), Doering et al.
patent: 4574465 (1986-03-01), Rao
Local Oxidation of Silicon by J. A. Appels et al. Philips Res. Repts 25, 118-132, 1970.
Deep Trench Isolated Cmos Devices by R. D. Rung et al., 1982 p. 237.

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