Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1996-02-29
1997-10-07
Zarabian, A.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36518901, G11C 800
Patent
active
056755481
ABSTRACT:
An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
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Akioka Takashi
Gotou Nobuyuki
Hiraishi Atsushi
Ide Akira
Iwamura Masahiro
Hitachi , Ltd.
Zarabian A.
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