Semiconductor integrated circuit having improved wiring in input

Details Semiconductor integrated circuit having improved wiring in input Semiconductor integrated circuit having improved wiring in input

1997-01-29

1998-03-03

Le, Vu A.

Static information storage and retrieval

Interconnection arrangements

36523008, 36518905, G11C 1300

Patent

active

057242810

ABSTRACT:
The input pads DQ0 to DQ3 and the input buffers DIB0 to DIB3 are connected to each other by means of the wires La or Lb. In the case where the memory cell array is of the .times.4 bit pattern, the input pads DQ0 to DQ3 are connected to the input terminals of the input buffers DIB0 to DIB3, respectively, via the wires La, whereas in the case where the memory cell array is of the .times.1 bit pattern, one of the input pads, that is, DQ0 is connected to each of the input terminals of the input buffers DIB0 to DIB3 via the wires Lb. The structures from the input buffers DIB0 to DIB3 to the memory cell arrays are the same and common to the .times.4 bit pattern and the .times.1 bit pattern, and therefore an increase in the driving performance of the transistors in the input buffers DIB0 to DIB3 can be suppressed.

REFERENCES:
patent: 5471157 (1995-11-01), McClure
patent: 5615166 (1997-03-01), Machida

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