Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2000-07-27
2003-08-05
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S202000, C257S204000, C257S205000, C257S207000, C257S208000, C257S210000, C257S211000
Reexamination Certificate
active
06603158
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, in which base cells are arrayed in first and second directions perpendicular to each other, fabricated according to a master slice method or a standard cell method.
2. Description of the Related Art
FIG.
14
(A) is a top view of a prior art base cell BCX in which gate lines are hatched (this applies to other figures).
The base cell BCX comprises an N-type well
10
indicated with a double dot and dash line, P-type diffused regions
11
,
12
and
13
arrayed in a column direction and formed in the N-type well
10
, and gate lines
14
and
15
formed above a channel between the P-type diffused regions
11
and
12
and above a channel between the P-type diffused regions
12
and
13
, respectively, with a gate insulating film, for example a gate oxide film, interposed between each channel and gate line. Further, the base cell BCX comprises N
+
-type well contact regions
16
and
17
formed in the N-type well
10
in such a manner that they sandwich the P-type diffused regions
11
to
13
as a whole. Likewise, the base cell BCX comprises a P-type well
20
indicated with a double dot and dash line next to the N-type well
10
, N type diffused regions
21
,
22
and
23
arrayed in a column direction and formed in the P-type well
20
, and gate lines
24
and
25
formed above a channel between the N-type diffused regions
21
and
22
, and above a channel between the N-type diffused regions
22
and
23
, respectively, with a gate insulating film interposed between each channel and gate line. P
+
-type well contact regions
26
and
27
are formed in the P-type well
20
in such a manner that they sandwich the N-type diffused regions
21
to
23
as a whole. At both ends of each of the gate lines
14
,
15
,
24
and
25
, there are gate contact regions for connecting through interlayer contacts and conductive lines.
For example, one NAND gate with two-input is constituted of one base cell BCX with connecting conductive lines in the cell in a first wiring layer and power supply lines in a second wiring layer. The N
+
-type well contact regions
16
and
27
are connected to a power supply line VDD and a ground line VSS, respectively, in the second wiring layer above the first wiring layer. In FIG.
14
(A), the VDD and VSS lines are represented by center lines thereof (a single dot and dash line) for simplicity.
Such base cells are arrayed in rows and columns on a semiconductor substrate to form, for example, a gate array according to a master slice method. In a row direction, base cells are arranged with no superimposition between adjacent cells. However, in a column direction, as shown in FIG.
14
(B), base cells are arranged with superimposing well contact regions adjacent to each other in a design.
Cell pitches of the gate array in row and column directions are 10G and 4G, respectively, wherein G, for example, 0.8 mm denotes a pitch of a grid in design. Interconnections between cells are implemented in a third wiring layer above the second wiring layer. Automatic interconnection design using a computer is performed along grid lines.
Since the base cell BCX has the construction in which the N
+
-type well contact regions
16
and
17
are formed in the N-type well
10
in such a manner that they sandwich the P-type diffused regions
11
to
13
, while the P
+
-type well contact regions
26
and
27
are formed in the P-type well
20
in such a manner that they sandwich the N-type diffused regions
21
to
23
, a cell size is larger, thereby reducing a degree of integration.
Further, the well contact regions
17
and
26
are useless.
Connections between cells are mainly implemented by conductive lines in a column direction. However, connections in a column direction cannot be implemented in the second wiring layer since the power supply lines VDD and VSS are formed in a row direction in the second wiring layer.
FIG.
15
(A) is a top view of another prior art base cell BCY.
In the base cell BCY, a gate line
34
serially passes above a channel between P-type diffused regions
11
and
12
A and above a channel between N-type diffused regions
21
and
22
A and similar to this, a gate line
35
serially passes above a channel between P-type diffused regions
12
A and
13
and above a channel between N-type diffused regions
22
A and
23
. With these series of the gate lines, a cell pitch of a gate array in a row direction is (8G+G′) as shown in FIG.
15
(B), and the cell pitch is shorter than that of 10G of FIG.
14
(B) by (2G−G′). For example, when G=0.8 mm and G′=1.0 mm, 2G−G′=0.6 mm. The reason why the cell pitch of the gate array in the row direction is not 9G but (8G+G′) is that when cells are arrayed in the row direction, there arise a need to ensure a margin between adjacent gate contact regions, which is required from design rules.
Further, instead of the N
+
-type well contact regions
16
and
17
of FIG.
14
(A), an N
+
-type well contact region
16
A is formed in the N-type well
10
under a place between gate contact regions
341
and
351
formed at one ends of the gate lines
34
and
35
, and similar to this, instead of the P
+
-type well contact regions
26
and
27
of FIG.
14
(A), a P
+
-type well contact region
26
A is formed in the P-type well
20
under a place between gate contact regions
342
and
352
formed at the other ends of the gate lines
34
and
35
. Since there arise a need to ensure margins between the N
+
-type well contact region
16
A and each of the gate contact regions
341
and
351
, which is required from design rules, widths of the diffused regions
12
A and
22
A in a column direction are necessary to be wider than those of other diffused regions. Hence, a cell pitch of a gate array in a column direction is (2G+G′) as shown in FIG.
15
(B). For this reason, a higher degree of integration was restricted.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit having a high-density base cell array.
In one aspect of the present invention, there is provided a semiconductor integrated circuit comprising base cells arrayed in first and second directions perpendicular to each other, each base cell comprising: an N-type well; a plurality of P-type regions formed in the N-type well and arrayed in the second direction; a P-type well arranged adjacent to the N-type well in the first direction; a plurality of N-type regions formed in the P-type well and arrayed in the second direction; gate lines each formed in the first direction with passing above a channel between adjacent two of the P-type regions and passing above a channel between adjacent two of the N-type regions, each of the gate lines not having gate contact regions at both ends thereof; an N-type well contact region formed in the N-type well on a side of a first directional end of one of the gate lines; a P-type well contact region formed in the P-type well on a side of an opposite first directional end of one of the gate lines; an intra-cell interconnections formed in a first wiring layer; a first power supply line connected to the N-type well contact region with passing in the second direction, the first power supply line formed in a second wiring layer above the first wiring layer; and a second power supply line connected to the P-type well contact region with passing in the second direction, the second power supply line formed in the second wiring layer.
With this aspect, since the widths of the P-type regions and N-type regions in the second direction can be same as each other, a cell pitch can be more shortened than the prior art, thereby enabling higher density of base cell array.
Further, since the power supply lines are formed in the second direction, interconnections between base cells in the second direction can be performed using the second wiring
Kajii Yoshio
Osajima Toru
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Lee Eddie
Lee Eugene
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