Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-02-19
2001-06-05
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S706000, C257S707000, C257S718000, C257S720000
Reexamination Certificate
active
06242807
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor integrated circuit having a multilayer writing structure, and more particularly to a semiconductor integrated circuit that can efficiently remove heat generated in a signal wiring layer located in an upper part of the multilayer structure.
BACKGROUND OF THE INVENTION
In the operation of circuits within LSI (large scale integration) a charge/discharge current for a circuit to drive the capacitance load of a next circuit flows through wiring, causing the wiring to generate heat due to its own resistance. In a major part of conventional semiconductor integrated circuits, the operating frequency is not more than 100 MHz, and the number of signal wiring layers constituting the multilayer wiring structure is two or three. For this reason, heat generation in the wiring has not been significant and hence has posed no serious problem as compared with that in transistors.
In recent years, however, the development of microfabrication techniques, circuits, layout designs and the like of LSI has resulted in rapid advance of an increase in operating speed of circuits, an increase in integration density, and an increase in number of wiring layers constituting multilayer wiring structures. This has led to increased heat generation in the wiring.
In LSI packages of larger power consumption involving significant heat generation, it is common practice to use an LSI cooling method wherein a heat sink or the like is connected to a silicon substrate on its backside and air is blown against the heat sink to cool the LSI. In this case, most of the heat generated from LSI is removed through the silicon substrate underlying the LSI. The heat generated in the wiring is released through two routes, one of which is such that heat is conveyed by the wiring per se and is released into the silicon substrate, and the other is such that heat travels through an interlayer film and is released into the silicon substrate. Therefore, when the wiring is located at an upper position, the distance between this wiring and the underlying silicon substrate is increased and, hence, heat is less likely to be conveyed to the silicon substrate. For this reason, the temperature rise due to heat generation created in the upper wiring is significant particularly in a multilayer wiring structure.
In order to increase the operation rate of the circuit, there is a trend toward an increase in the thickness of interlayer film provided between wiring layers to lower the wiring capacitance. The increased interlayer film thickness, however, increases the distance between the upper wiring layer and the silicon substrate. This accelerates the temperature rise due to heat generation of the wiring.
The increased wiring temperature is likely to create breaking or the like of the wiring due to electromigration, resulting in deteriorated reliability. In general, the deterioration in wiring due to electromigration indexically increases with increasing the temperature. For this reason, avoiding temperature rise of the wiring has become strongly required in the art. Regarding the temperature rise of the wiring, for example, in a five-layer signal wiring layer under certain conditions, experimental data have been reported wherein current flow of about 5×10
5
A/cm
2
in current density J through each signal wiring layer develops a wiring temperature rise of about 90° C. due to heat generation of the wiring per se.
In order to solve the above problems, for example, Japanese Patent Laid-Open No. 129725/1997 discloses a semiconductor integrated circuit. In this conventional semiconductor integrated circuit, a specialty dummy through-hole extending from the uppermost wiring layer to the lowermost wiring layer is provided, and the dummy through-hole is packed with an insulating material having high thermal conductivity to efficiently dissipate heat.
In the conventional semiconductor integrated circuit, the provision of the dummy hole requires, in addition to the provision of the step of producing wiring for constructing a desired circuit, specialty steps, that is, the step of forming a dummy hole for heat dissipation and the step of packing the dummy hole with an insulating material having high thermal conductivity. This increases the number of steps required for the production, posing problems of production cost and the like.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a semiconductor integrated circuit that can remove heat generated in the wiring while preventing an increase in the number of production steps to realize high reliability.
According to the first feature of the invention, a semiconductor integrated circuit having a multilayer wiring structure, comprises: a plurality of signal wiring layers; and an electrically nonconnected heat sink wiring extended from a predetermined wiring layer to a silicon substrate underlying the predetermined signal wiring layer.
Preferably, a PN junction is provided in the silicon substrate in its portion in contact with the heat sinking wiring.
The heat sinking wiring is preferably provided based on the magnitude of a current flowing through the signal wiring layer.
The heat sinking wiring is preferably in contact with the silicon substrate while avoiding the contact of the heat sink wiring with an oxide layer provided on the surface of the silicon substrate.
The predetermined wiring layer is preferably the uppermost signal wiring layer.
The silicon substrate underlying the predetermined signal wiring layer is preferably a silicon substrate as the lowermost layer.
REFERENCES:
patent: 5698897 (1997-12-01), Nashimoto et al.
patent: 5792677 (1998-08-01), Reddy et al.
patent: 54-69394 (1979-06-01), None
patent: 63-78553 (1988-04-01), None
patent: 9-129725 (1997-05-01), None
patent: 9-213696 (1997-08-01), None
Abraham Fetsum
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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