Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-05-10
2001-09-25
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S900000, C438S910000, C438S903000, C307S056000, C307S064000, C307S080000, C307S402000, C327S544000
Reexamination Certificate
active
06294404
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit system, and more specifically, it relates to a structure for reducing power consumption.
2. Description of the Prior Art
A data hold mode in a conventional asynchronous SRAM (SRAM: Static Random Access Memory) is described with reference to FIG.
35
. In order to set the SRAM in the data hold mode, a chip selection signal /CS is set in a nonselective state (high) for taking a setup period tsu(PD) and a power supply voltage Vdd is stepped down to a data hold mode voltage. The SRAM is set in the data hold mode having low power consumption due to the step-down of the voltage applied thereto.
In order to return the SRAM from the data hold mode to an operating mode, the power supply voltage Vdd is returned to an operating voltage and the chip selection signal /CS is returned to a selective state (set low) through a recovery time trec(PD).
FIGS. 36A and 36B
illustrate exemplary input circuits
200
and
201
included in the asynchronous SRAM. The input circuit
200
includes PMOS transistors P
50
and P
51
and NMOS transistors N
50
and N
51
. The transistors P
50
, N
50
and N
51
are connected between a power supply node Vdd receiving the operating voltage and ground power. The gates of the transistors P
50
and N
50
receive an input signal to be captured. A signal from a node Z
50
between the transistors P
50
and N
50
is transferred to an internal circuit. The gate of the transistor N
51
receives an internal chip selection signal (internal CS signal) corresponding to a chip selection signal /CS. The transistor P
51
is connected between the node Z
50
and a power supply node Vdd, and receives the internal CS signal in the gate thereof.
The input circuit
201
includes PMOS transistors P
52
and P
53
and NMOS transistors N
52
and N
53
. The transistors P
52
, P
53
and N
53
are connected between a power supply node Vdd and ground power. The gates of the transistors P
53
and N
53
receive an input signal to be captured. A signal from a node Z
51
between the transistors P
53
and N
53
is transferred to an internal circuit. The gate of the transistor P
52
receives a signal (internal /CS signal) obtained by inverting an internal chip selection signal. The transistor N
52
is connected between the node Z
51
and the ground power, and receives the internal /CS signal in the gate thereof. When a chip selection signal is nonselective, the input initial stage is inactivated so that no current flows regardless of the input signal.
A synchronous SRAM has a snooze mode, in order to suppress power consumption. The snooze mode is now described with reference to FIG.
37
.
FIG. 37
shows a clock signal CLK, a snooze mode signal ZZ, an address status controller signal /ADSC, a write enable signal /WE and an output enable signal /OE as input signals.
In order to set the SRAM in the snooze mode, the control signals excluding the snooze mode signal ZZ are inactivated and thereafter the snooze mode signal ZZ is activated (high). The SRAM enters a snooze state after a lapse of a setup time.
In the snooze state, fluctuation of the signals excluding the output enable signal /OE exerts no influence on the SRAM. In the smooth mode, the SRAM has low power consumption regardless of external signals.
In order to return the SRAM from the snooze mode to an operating mode, the snooze mode signal ZZ is set low. The synchronous SRAM becomes operable after a lapse of a recovery time.
FIGS. 38A and 38B
illustrate exemplary input circuits
202
and
203
having a snooze mode function included in the synchronous SRAM. The input circuit
202
includes PMOS transistors P
54
and P
55
and NMOS transistors N
54
and N
55
. The transistors P
54
, N
54
and N
55
are connected between a power supply node Vdd and ground power. The gates of the transistors P
54
and N
54
receive an input signal to be captured. A signal from a node Z
52
between the transistors P
54
and N
54
is transferred to an internal circuit. The gate of the transistor N
55
receives an internal snooze mode signal (internal ZZ signal) corresponding to the snooze mode signal ZZ. The transistor P
55
is connected between the node Z
52
and a power supply node Vdd, and receives the internal ZZ signal in the gate thereof.
The input circuit
203
includes PMOS transistors P
56
and P
57
and NMOS transistors N
56
and N
57
. The transistors P
56
, P
57
and N
57
are connected between a power supply node Vdd and ground power. The gates of the transistors P
57
and N
57
receive an input signal to be captured. A signal from a node Z
53
between the transistors P
57
and N
57
is transferred to an internal circuit. The gate of the transistor P
56
receives a signal (internal /ZZ signal) obtained by inverting an internal snooze mode signal. The transistor N
56
is connected between the node Z
53
and the ground power, and receives the internal /ZZ signal in its gate. In the snooze mode, the input initial stage is inactivated so that no current flows regardless of the input signal. The chip selection signal /CS and the snooze mode signal ZZ may be ANDed when generating the internal ZZ signal.
A power down mode of a synchronous DRAM (DRAM: Dynamic Random Access Memory) is now described with reference to FIG.
39
.
FIG. 39
shows a clock signal CLK and a clock enable signal CKE as input signals.
In the power down mode, the clock enable signal CKE is set low thereby inactivating an internal clock of the device and suppressing power consumption of the device.
Thus, both of synchronous and asynchronous memory chips have a function for enabling suppression of power consumption.
However, the conventional synchronous SRAM still consumes power of about several mW in the snooze mode, and reduction of power consumption is insufficient for applying the synchronous SRAM to a portable terminal or the like.
In the asynchronous SRAM, power consumption can be suppressed due to the data hold mode. In actual operation, however, the SRAM receives no signal for performing a synchronous operation and hence an ATD (address transition detect) circuit or a DTD (data transition detect) circuit must be provided in the SRAM for generating internal write and read control signals. Such a specific circuit increases the operating current as a result. Further, it is difficult to design a circuit finely controlling the internal timing.
In addition, a signal forming the basis of a read timing is internally generated. Therefore, a sense amplifier based on a current mirror type having a low possibility of false reading is employed so that data can be reliably read from a memory cell in consideration of timing deviation. In this case, however, current must be regularly fed to result in feeding of excess current.
In the synchronous SDRAM, power consumption must be reduced not only in the power down mode but also in an operating mode.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit and a semiconductor integrated circuit system capable of reducing power consumption in a standby state as well as in an operating state.
A semiconductor integrated circuit according to an aspect of the present invention comprises a static semiconductor memory device selected in response to a chip selection signal for operating in synchronization with a clock signal and a controller for controlling operations of the static semiconductor memory device, and the controller switches the static semiconductor memory device to a power down mode by switching the chip selection signal to a nonselective state and thereafter stepping down a power voltage supplied to the static semiconductor memory device from an operating power supply potential to a standby potential.
According to the aforementioned semiconductor integrated circuit, a synchronous SRAM can be set in a standby state having extremely low power consumption by switching the chip selection signal to the nonselective state an
Elms Richard
Luu Pho
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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