Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
2000-01-07
2002-03-26
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C257S207000, C438S129000
Reexamination Certificate
active
06362497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit having a plurality of power source systems, and more specifically, to a semiconductor integrated circuit having an ESD/EOS protection circuit for each of the power sources system.
2. Description of the Related Art
FIG. 5
shows the configuration of a semiconductor integrated circuit (IC) with a single power source system according to the related art. In this figure, the semiconductor integrated circuit
21
has a core area
22
and an I/O region
23
. A logic circuit such as a gate array or embedded array is formed in the core area
22
. An electrostatic discharge (ESD) and electrical overstress (EOS) protection circuit is situated in the I/O region
23
along with an Input/Output circuit such as an I/O buffer in order to protect the semiconductor integrated circuit
21
against external electrostatic discharges and electrical stress. A thick power source line B connected to the power source and a ground line G are wired in the I/O region
23
for the I/O buffer and the ESD/EOS protection circuit. An I/O pad (not shown) for the input and output of signals to and from the semiconductor chip is wired in the I/O region
23
or to the outside of the I/O region
23
.
FIG. 6
shows the ESD/EOS protection circuit. In this figure, the connection points on the Input /Output pad P
21
and the I/O buffer are connected to the power source line B at an electrical potential of Vdd via a protective diode D
21
, and to the ground line G at an electrical potential of Gnd via another protective diode D
22
. A number of power source system protection circuit elements, such as diode D
23
, condenser C
21
, and MOS transistors Tr
21
and Tr
22
, are distributed and connected between the power source line B and the ground line G. There may also be protective diodes (not shown) connected to the power source line B and the ground line G from the Input/Output pads of the Input/Output circuits in the same manner as the protective diodes D
21
and D
22
.
In the ESD/EOS protection circuit, a high positive voltage applied to the Input/Output pad P
21
is sent to the power source line B though the protective diode D
21
and absorbed by the power source system protective elements connected between the power source line B and the ground line G. A high negative potential applied to the Input/Output pad P
21
is sent to the ground line G through the protective diode D
22
and absorbed by the power source system protective elements. An irregular voltage applied to the power source line B and the ground line G is also absorbed by the power source protective elements.
The ESD/EOS protection circuit shown in
FIG. 6
is situated in the I/O region
23
shown in FIG.
5
and is configured so as to perform ESD/EOS protection in a known manner. These structures are used by semiconductor integrated circuits formed with the power sources of several type. However, ESD/EOS protection circuits also have to be formed in semiconductor integrated circuits with a plurality of power source systems, such as circuits shown in FIG.
7
and FIG.
8
.
FIG. 7
shows a semiconductor integrated circuit
21
with four power source systems. In
FIG. 7
, an ESD/EOS protection circuit is formed in the I/O region
23
along with an Input/Output circuit such as an Input/Output buffer. The power source lines for the power source systems are B-
1
through B-
4
and the ground line is G. In the prior art structure, these power source lines B-
1
through B-
4
and the ground line G must have narrow line widths in order to be formed in the I/O region
23
. As a result, the performance of the ESD/EOS protection circuit is often unsatisfactory.
FIG. 8
shows another semiconductor integrated circuit
21
with four power source systems. In
FIG. 8
, the I/O region is partitioned into I/O regions
23
-
1
through
23
-
4
corresponding to each of the power source systems. An ESD/EOS protection circuit is formed in each one of these partitioned regions along with an Input/Output circuit such as an Input/Output buffer. There is a power source line and a ground line in each one of these partitioned regions. For example, power source line B-
1
′ and ground line G-
1
are situated in I/O region
23
-
1
. In this configuration, the line widths of the power source lines and ground lines in these partitioned regions are adequate, but the area in which the protection circuits for each one of the power source systems can be formed is greatly reduced.
For the ESD/EOS protection to function properly, a certain number of protective elements must be provided. This number is unrelated to the number of Input/Output lines to be protected. The number of protective elements that can be formed is largely proportional to the area of the I/O region. Because the area of the partitioned regions in
FIG. 8
is small, an adequate number of protective elements cannot be formed for each power source system, and ESD/EOS protection does not function properly.
SUMMARY OF THE INVENTION
Thus, when ESD/EOS protection circuits are formed in semiconductor integrated circuits with a plurality of power source systems, either the power source lines and ground lines are too narrow and the ESD/EOS protection does not function as desired, or the number of protective elements for each power source system is inadequate and the ESD/EOS protection does not function properly.
Accordingly, the present invention is directed to a semiconductor integrated circuit having a plurality of power source systems with ESD/EOS protection that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor integrated circuit having a plurality of power source systems with adequate ESD/EOS protection, by constructing an ESD/EOS protection circuit in the semiconductor integrated circuit and partitioning the arrangement of power source system protective elements necessary to perform ESD/EOS protection irrespective of the number of protective diodes and Inputs/Outputs proportional to the number of Input/Output circuits.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a semiconductor integrated circuit having a substrate and a logic circuit and a plurality of power source systems formed in the substrate, the semiconductor IC including an I/O region partitioned into a plurality of partitioned I/O regions each having at least a part of one of the plurality of power source systems formed therein; a core area distinct from the I/O region and having the logic circuit formed therein; and an ESD/EOS protection circuit for each power source system, the ESD/EOS protection circuit having power source system protective elements, wherein at least some of the power source system protective elements of at least some of the ESD/EOS protection circuits are formed in the partitioned I/O region for the corresponding power source system, and at least some of the power source system protective elements of at least some of the ESD/EOS protection circuits are formed in the core area.
In such a semiconductor integrated circuits having a plurality of power source systems, the I/O region is partitioned for each one of the power source systems, and the formation of partitioned I/O regions allows the power source lines and ground lines for each one of the partitioned I/O regions to have sufficient width to provide adequate protection.
The ESD/EOS protection circuit for each power source system is config
Hogan & Hartson L.L.P.
Prenty Mark V.
Rohm & Co., Ltd.
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